ADC memory map (continued)Absoluteaddress(hex)Register name Width(in bits) Access Reset value Section/page4003_B020 Status and Control Register 2 (ADC0_SC2) 32 R/W 0000_0000h 28.3.6/4704003_B024 Status and Control Register 3 (ADC0_SC3) 32 R/W 0000_0000h 28.3.7/4724003_B028 ADC Offset Correction Register (ADC0_OFS) 32 R/W 0000_0004h 28.3.8/4744003_B02C ADC Plus-Side Gain Register (ADC0_PG) 32 R/W 0000_8200h 28.3.9/4744003_B030 ADC Minus-Side Gain Register (ADC0_MG) 32 R/W 0000_8200h 28.3.10/4754003_B034 ADC Plus-Side General Calibration Value Register(ADC0_CLPD) 32 R/W 0000_000Ah 28.3.11/4754003_B038 ADC Plus-Side General Calibration Value Register(ADC0_CLPS) 32 R/W 0000_0020h 28.3.12/4764003_B03C ADC Plus-Side General Calibration Value Register(ADC0_CLP4) 32 R/W 0000_0200h 28.3.13/4764003_B040 ADC Plus-Side General Calibration Value Register(ADC0_CLP3) 32 R/W 0000_0100h 28.3.14/4774003_B044 ADC Plus-Side General Calibration Value Register(ADC0_CLP2) 32 R/W 0000_0080h 28.3.15/4774003_B048 ADC Plus-Side General Calibration Value Register(ADC0_CLP1) 32 R/W 0000_0040h 28.3.16/4784003_B04C ADC Plus-Side General Calibration Value Register(ADC0_CLP0) 32 R/W 0000_0020h 28.3.17/4784003_B054 ADC Minus-Side General Calibration Value Register(ADC0_CLMD) 32 R/W 0000_000Ah 28.3.18/4794003_B058 ADC Minus-Side General Calibration Value Register(ADC0_CLMS) 32 R/W 0000_0020h 28.3.19/4794003_B05C ADC Minus-Side General Calibration Value Register(ADC0_CLM4) 32 R/W 0000_0200h 28.3.20/4804003_B060 ADC Minus-Side General Calibration Value Register(ADC0_CLM3) 32 R/W 0000_0100h 28.3.21/4804003_B064 ADC Minus-Side General Calibration Value Register(ADC0_CLM2) 32 R/W 0000_0080h 28.3.22/4814003_B068 ADC Minus-Side General Calibration Value Register(ADC0_CLM1) 32 R/W 0000_0040h 28.3.23/4814003_B06C ADC Minus-Side General Calibration Value Register(ADC0_CLM0) 32 R/W 0000_0020h 28.3.24/48228.3.1 ADC Status and Control Registers 1 (ADCx_SC1n)SC1A is used for both software and hardware trigger modes of operation.To allow sequential conversions of the ADC to be triggered by internal peripherals, theADC can have more then one status and control register: one for each conversion. TheSC1B–SC1n registers indicate potentially multiple SC1 registers for use only in hardwareRegister definitionKL25 Sub-Family Reference Manual, Rev. 3, September 2012462 Freescale Semiconductor, Inc.
