28.3.18 ADC Minus-Side General Calibration Value Register(ADCx_CLMD)The Minus-Side General Calibration Value (CLMx) registers contain calibrationinformation that is generated by the calibration function. These registers contain sevencalibration values of varying widths: CLM0[5:0], CLM1[6:0], CLM2[7:0], CLM3[8:0],CLM4[9:0], CLMS[5:0], and CLMD[5:0]. CLMx are automatically set when the self-calibration sequence is done, that is, CAL is cleared. If these registers are written by theuser after calibration, the linearity error specifications may not be met.Address: 4003_B000h base + 54h offset = 4003_B054hBit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0R 0 CLMDWReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0ADCx_CLMD field descriptionsField Description31–6ReservedThis field is reserved.This read-only field is reserved and always has the value 0.5–0CLMDCalibration Value28.3.19 ADC Minus-Side General Calibration Value Register(ADCx_CLMS)For more information, see CLMD register description.Address: 4003_B000h base + 58h offset = 4003_B058hBit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0R 0 CLMSWReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0ADCx_CLMS field descriptionsField Description31–6ReservedThis field is reserved.This read-only field is reserved and always has the value 0.5–0CLMSCalibration ValueChapter 28 Analog-to-Digital Converter (ADC)KL25 Sub-Family Reference Manual, Rev. 3, September 2012Freescale Semiconductor, Inc. 479
