14.4 I/O retentionWhen in LLS mode, the I/O pins are held in their input or output state. Upon wakeup, thePMC is re-enabled, goes through a power up sequence to full regulation, and releases thelogic from state retention mode. The I/O are released immediately after a wakeup or resetevent. In the case of LLS exit via a RESET pin, the I/O default to their reset state.When in VLLS modes, the I/O states are held on a wakeup event (with the exception ofwakeup by reset event) until the wakeup has been acknowledged via a write to theACKISO bit. In the case of VLLS exit via a RESET pin, the I/O are released and defaultto their reset state. In this case, no write to the ACKISO is needed.14.5 Memory map and register descriptionsPMC register details follow.NOTEDifferent portions of PMC registers are reset only by particularreset types. Each register's description provides details. Formore information about the types of reset on this chip, refer tothe Reset section details.The PMC registers can be written only in supervisor mode.Write accesses in user mode are blocked and will result in a buserror.PMC memory mapAbsoluteaddress(hex)Register name Width(in bits) Access Reset value Section/page4007_D000 Low Voltage Detect Status And Control 1 register(PMC_LVDSC1) 8 R/W 10h 14.5.1/2404007_D001 Low Voltage Detect Status And Control 2 register(PMC_LVDSC2) 8 R/W 00h 14.5.2/2414007_D002 Regulator Status And Control register (PMC_REGSC) 8 R/W 04h 14.5.3/242Chapter 14 Power Management Controller (PMC)KL25 Sub-Family Reference Manual, Rev. 3, September 2012Freescale Semiconductor, Inc. 239
