Address: 4007_F000h base + 4h offset = 4007_F004hBit 7 6 5 4 3 2 1 0Read 0 RSTFLTSS RSTFLTSRWWriteReset 0 0 0 0 0 0 0 0RCM_RPFC field descriptionsField Description7–3ReservedThis field is reserved.This read-only field is reserved and always has the value 0.2RSTFLTSSReset Pin Filter Select in Stop ModeSelects how the reset pin filter is enabled in Stop and VLPS modes , and also during LLS and VLLSmodes. On exit from VLLS mode, this bit should be reconfigured before clearing ACKISO in the PMC.0 All filtering disabled1 LPO clock filter enabled1–0RSTFLTSRWReset Pin Filter Select in Run and Wait ModesSelects how the reset pin filter is enabled in run and wait modes.00 All filtering disabled01 Bus clock filter enabled for normal operation10 LPO clock filter enabled for normal operation11 Reserved16.2.4 Reset Pin Filter Width register (RCM_RPFW)NOTEThe reset values of the bits in the RSTFLTSEL field are forChip POR only. They are unaffected by other reset types.Address: 4007_F000h base + 5h offset = 4007_F005hBit 7 6 5 4 3 2 1 0Read 0 RSTFLTSELWriteReset 0 0 0 0 0 0 0 0RCM_RPFW field descriptionsField Description7–5ReservedThis field is reserved.This read-only field is reserved and always has the value 0.4–0RSTFLTSELReset Pin Filter Bus Clock SelectSelects the reset pin bus clock filter width.Table continues on the next page...Chapter 16 Reset Control Module (RCM)KL25 Sub-Family Reference Manual, Rev. 3, September 2012Freescale Semiconductor, Inc. 269
