38.4.3 Address matchingAll received addresses can be requested in 7-bit or 10-bit address format.• AD[7:1] in Address Register 1, which contains the I2C primary slave address, alwaysparticipates in the address matching process. It provides a 7-bit address.• If the ADEXT bit is set, AD[10:8] in Control Register 2 participates in the addressmatching process. It extends the I2C primary slave address to a 10-bit address.Additional conditions that affect address matching include:• If the GCAEN bit is set, general call participates the address matching process.• If the ALERTEN bit is set, alert response participates the address matching process.• If the SIICAEN bit is set, Address Register 2 participates in the address matchingprocess.• If the Range Address register is programmed to a nonzero value, the range addressitself participates in the address matching process.• If the RMEN bit is set, any address within the range of values of Address Register 1and the Range Address register participates in the address matching process. TheRange Address register must be programmed to a value greater than the value ofAddress Register 1.When the I2C module responds to one of these addresses, it acts as a slave-receiver andthe IAAS bit is set after the address cycle. Software must read the Data register after thefirst byte transfer to determine that the address is matched.38.4.4 System management bus specificationSMBus provides a control bus for system and power management related tasks. A systemcan use SMBus to pass messages to and from devices instead of tripping individualcontrol lines. Removing the individual control lines reduces pin count. Acceptingmessages ensures future expandability. With the system management bus, a device canprovide manufacturer information, tell the system what its model/part number is, save itsstate for a suspend event, report different types of errors, accept control parameters, andreturn its status.38.4.4.1 TimeoutsThe TTIMEOUT,MIN parameter allows a master or slave to conclude that a defective deviceis holding the clock low indefinitely or a master is intentionally trying to drive devicesoff the bus. The slave device must release the bus (stop driving the bus and let SCL andChapter 38 Inter-Integrated Circuit (I2C)KL25 Sub-Family Reference Manual, Rev. 3, September 2012Freescale Semiconductor, Inc. 709
