24.4.1.1 MCG modes of operationThe MCG operates in one of the following modes.NoteThe MCG restricts transitions between modes. For thepermitted transitions, see Figure 24-16.Table 24-18. MCG modes of operationMode DescriptionFLL Engaged Internal(FEI)FLL engaged internal (FEI) is the default mode of operation and is entered when all the followingcondtions occur:• C1[CLKS] bits are written to 00• C1[IREFS] bit is written to 1• C6[PLLS] bit is written to 0In FEI mode, MCGOUTCLK is derived from the FLL clock (DCOCLK) that is controlled by the 32kHz Internal Reference Clock (IRC). The FLL loop will lock the DCO frequency to the FLL factor, asselected by C4[DRST_DRS] and C4[DMX32] bits, times the internal reference frequency. See theC4[DMX32] bit description for more details. In FEI mode, the PLL is disabled in a low-power stateunless C5[PLLCLKEN0] is set.FLL Engaged External(FEE)FLL engaged external (FEE) mode is entered when all the following conditions occur:• C1[CLKS] bits are written to 00• C1[IREFS] bit is written to 0• C1[FRDIV] must be written to divide external reference clock to be within the range of 31.25kHz to 39.0625 kHz• C6[PLLS] bit is written to 0In FEE mode, MCGOUTCLK is derived from the FLL clock (DCOCLK) that is controlled by theexternal reference clock. The FLL loop will lock the DCO frequency to the FLL factor, as selected byC4[DRST_DRS] and C4[DMX32] bits, times the external reference frequency, as specified byC1[FRDIV] and C2[RANGE0]. See the C4[DMX32] bit description for more details. In FEE mode,the PLL is disabled in a low-power state unless C5[PLLCLKEN0] is set.FLL Bypassed Internal(FBI)FLL bypassed internal (FBI) mode is entered when all the following conditions occur:• C1[CLKS] bits are written to 01• C1[IREFS] bit is written to 1• C6[PLLS] is written to 0• C2[LP] is written to 0In FBI mode, the MCGOUTCLK is derived either from the slow (32 kHz IRC) or fast (4 MHz IRC)internal reference clock, as selected by the C2[IRCS] bit. The FLL is operational but its output is notused. This mode is useful to allow the FLL to acquire its target frequency while the MCGOUTCLK isdriven from the C2[IRCS] selected internal reference clock. The FLL clock (DCOCLK) is controlledby the slow internal reference clock, and the DCO clock frequency locks to a multiplication factor, asselected by C4[DRST_DRS] and C4[DMX32] bits, times the internal reference frequency. See theC4[DMX32] bit description for more details. In FBI mode, the PLL is disabled in a low-power stateunless C5[PLLCLKEN0] is set.Table continues on the next page...Chapter 24 Multipurpose Clock Generator (MCG)KL25 Sub-Family Reference Manual, Rev. 3, September 2012Freescale Semiconductor, Inc. 385
