6.2.1 Power-on reset (POR)When power is initially applied to the MCU or when the supply voltage drops below thepower-on reset re-arm voltage level (VPOR), the POR circuit causes a POR resetcondition.As the supply voltage rises, the LVD circuit holds the MCU in reset until the supply hasrisen above the LVD low threshold (VLVDL). The POR and LVD bits in reset statusregister are set following a POR.6.2.2 System reset sourcesResetting the MCU provides a way to start processing from a known set of initialconditions. System reset begins with the on-chip regulator in full regulation and systemclocking generation from an internal reference. When the processor exits reset, itperforms the following:• Reads the start SP (SP_main) from vector-table offset 0• Reads the start PC from vector-table offset 4• LR is set to 0xFFFF_FFFFThe on-chip peripheral modules are disabled and the non-analog I/O pins are initiallyconfigured as disabled. The pins with analog functions assigned to them default to theiranalog function after reset.During and following a reset, the SWD pins have their associated input pins configuredas:• SWD_CLK in pull-down (PD)• SWD_DIO in pull-up (PU)6.2.2.1 External pin reset (RESET)This pin is open drain and has an internal pullup device. Asserting RESET wakes thedevice from any mode.The RESET pin can be disabled by programming RESET_PIN_CFG option bit to 0.When this option selected, there could be a short period of contention during a POR rampwhere the device drives the pin out low prior to establishing the setting of this option andreleasing the RESET function on the pin.ResetKL25 Sub-Family Reference Manual, Rev. 3, September 2012128 Freescale Semiconductor, Inc.
