• The low voltage detect flag (LVDF) operates in a level sensitive manner. The LVDFbit is set when the supply voltage falls below the selected trip point (VLVD). TheLVDF bit is cleared by writing one to the LVDACK bit, but only if the internalsupply has returned above the trip point; otherwise, the LVDF bit remains set.• The low voltage warning flag (LVWF) operates in a level sensitive manner. TheLVWF bit is set when the supply voltage falls below the selected monitor trip point(VLVW). The LVWF bit is cleared by writing one to the LVWACK bit, but only ifthe internal supply has returned above the trip point; otherwise, the LVWF bitremains set.14.3.1 LVD reset operationBy setting the LVDRE bit, the LVD generates a reset upon detection of a low voltagecondition. The low voltage detection threshold is determined by the LVDV bits. After anLVD reset occurs, the LVD system holds the MCU in reset until the supply voltage risesabove this threshold. The LVD bit in the SRS register is set following an LVD or power-on reset.14.3.2 LVD interrupt operationBy configuring the LVD circuit for interrupt operation (LVDIE set and LVDRE clear),LVDSC1[LVDF] is set and an LVD interrupt request occurs upon detection of a lowvoltage condition. The LVDF bit is cleared by writing one to the LVDSC1[LVDACK]bit.14.3.3 Low-voltage warning (LVW) interrupt operationThe LVD system contains a low-voltage warning flag (LVWF) to indicate that the supplyvoltage is approaching, but is above, the LVD voltage. The LVW also has an interrupt,which is enabled by setting the LVDSC2[LVWIE] bit. If enabled, an LVW interruptrequest occurs when the LVWF is set. LVWF is cleared by writing one to theLVDSC2[LVWACK] bit.The LVDSC2[LVWV] bits select one of four trip voltages:• Highest: VLVW4• Two mid-levels: VLVW3 and VLVW2• Lowest: VLVW1Low-voltage detect (LVD) systemKL25 Sub-Family Reference Manual, Rev. 3, September 2012238 Freescale Semiconductor, Inc.
