• 32-bit prefetch speculation buffer for program flash accesses with controls forinstruction/data access• 4-way, 4-set, 32-bit line size program flash memory cache for a total of sixteen32-bit entries with invalidation control26.2 Modes of operationThe FMC operates only when a bus master accesses the program flash memory. In termsof chip power modes:• The FMC operates only in run and wait modes, including VLPR and VLPW modes.• For any power mode where the program flash memory cannot be accessed, the FMCis disabled.26.3 External signal descriptionThe FMC has no external (off-chip) signals.26.4 Memory map and register descriptionsThe MCM's programming model provides control and configuration of the FMC'sfeatures. For details, see the description of the MCM's Platform Control Register(PLACR).26.5 Functional descriptionThe FMC is a flash acceleration unit with flexible buffers for user configuration. Besidesmanaging the interface between bus masters and the program flash memory, the FMC canbe used to customize the program flash memory cache and buffer to provide single-cyclesystem clock data access times. Whenever a hit occurs for the prefetch speculation bufferor the cache (when enabled), the requested data is transferred within a single systemclock.Upon system reset, the FMC is configured as follows:• Flash cache is enabled• Instruction speculation and caching are enabledModes of operationKL25 Sub-Family Reference Manual, Rev. 3, September 2012416 Freescale Semiconductor, Inc.
