21.1.2 General operationThe slave devices connected to the peripheral bridge are modules which contain aprogramming model of control and status registers. The system masters read and writethese registers through the peripheral bridge. The peripheral bridge performs a busprotocol conversion of the master transactions and generates the following as inputs tothe peripherals:• Module enables• Module addresses• Transfer attributes• Byte enables• Write dataThe peripheral bridge selects and captures read data from the peripheral interface andreturns it to the crossbar switch.The register maps of the peripherals are located on 4-KB boundaries. Each peripheral isallocated one or more 4-KB block(s) of the memory map.The AIPS-Lite module uses the accessed peripheral's data width to perform proper databyte lane routing; bus decomposition (bus sizing) is performed when the access size islarger than the peripheral's data width.21.2 Functional descriptionThe peripheral bridge functions as a bus protocol translator between the crossbar switchand the slave peripheral bus.The peripheral bridge manages all transactions destined for the attached slave devices andgenerates select signals for modules on the peripheral bus by decoding accesses withinthe attached address space.By default, reads and writes on the crossbar side of the peripheral bridge take two data-phase cycles. On the IPS side, accesses complete in one cycle. If wait states are insertedby the slave peripheral, access time will be extended accordingly.21.2.1 Access supportAll combinations of access size and peripheral data port width are supported. An accessthat is larger than the target peripheral's data width will be decomposed to multiple,smaller accesses. Bus decomposition is terminated by a transfer error caused by an accessto an empty register area.Functional descriptionKL25 Sub-Family Reference Manual, Rev. 3, September 2012336 Freescale Semiconductor, Inc.
