2.4.1 ARM® Cortex™-M0+ Core ModulesThe following core modules are available on this device.Table 2-2. Core modulesModule DescriptionARM® Cortex™-M0+ The ARM® Cortex™-M0+ is the newest member of the Cortex M Series ofprocessors targeting microcontroller applications focused on very cost sensitive,deterministic, interrupt driven environments. The Cortex M0+ processor is basedon the ARMv6 Architecture and Thumb®-2 ISA and is 100% instruction setcompatible with its predecessor, the Cortex-M0 core, and upward compatible toCortex-M3 and M4 cores.NVIC The ARMv6-M exception model and nested-vectored interrupt controller (NVIC)implement a relocatable vector table supporting many external interrupts, a singlenon-maskable interrupt (NMI), and priority levels.The NVIC replaces shadow registers with equivalent system and simplifiedprogrammability. The NVIC contains the address of the function to execute for aparticular handler. The address is fetched via the instruction port allowing parallelregister stacking and look-up. The first sixteen entries are allocated to ARMinternal sources with the others mapping to MCU-defined interrupts.AWIC The primary function of the Asynchronous Wake-up Interrupt Controller (AWIC) isto detect asynchronous wake-up events in stop modes and signal to clock controllogic to resume system clocking. After clock restart, the NVIC observes thepending interrupt and performs the normal interrupt or event processing.Single-cycle I/O Port For high-speed, single-cycle access to peripherals, the Cortex-M0+ processorimplements a dedicated single-cycle I/O port.Debug interfaces Most of this device's debug is based on the ARM CoreSight™ architecture. Onedebug interface is supported:• Serial Wire Debug (SWD)2.4.2 System ModulesThe following system modules are available on this device.Table 2-3. System modulesModule DescriptionSystem integration module (SIM) The SIM includes integration logic and several module configuration settings.System mode controller The SMC provides control and protection on entry and exit to each power mode,control for the Power management controller (PMC), and reset entry and exit forthe complete MCU.Power management controller (PMC) The PMC provides the user with multiple power options. Multiple modes aresupported that allow the user to optimize power consumption for the level offunctionality needed. Includes power-on-reset (POR) and integrated low voltagedetect (LVD) with reset (brownout) capability and selectable LVD trip points.Miscellaneous control module (MCM) The MCM includes integration logic and details.Table continues on the next page...Module functional categoriesKL25 Sub-Family Reference Manual, Rev. 3, September 201240 Freescale Semiconductor, Inc.
