NXP Semiconductors MCF5272 ColdFire manuals
MCF5272 ColdFire
Table of contents
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- Table Of Contents
- MCF5272 ColdFire ® Integrated Microprocessor User's Manual,
- Overview
- general information
- acronyms and abbreviations
- MCF5272 Key Features
- MCF5272 Block Diagram
- MCF5272 Architecture
- System Integration Module (SIM)
- Power Management
- Timer Module
- Pulse-Width Modulation (PWM) Unit
- Features and Enhancements
- ColdFire Pipeline
- ColdFire Multiply-Accumulate Functionality Diagram
- Hardware Divide Unit
- ColdFire Programming Model
- Condition Code Register (CCR)
- MAC Programming Model
- Status Register (SR)
- Cache Control Register (CACR)
- Organization of Integer Data Formats in Data Registers
- Memory Operand Addressing
- Addressing Mode Summary
- Instruction Set Summary
- Supervisor-Mode Instruction Set Summary
- Instruction Timing
- MOVE Instruction Execution Times
- Move Long Execution Times
- Execution Timings—One-Operand Instructions
- Miscellaneous Instruction Execution Times
- Branch Instruction Execution Times
- Exception Vector Assignments
- Exception Stack Frame Form
- Processor Exceptions
- ColdFire MAC Multiplication and Accumulation
- General Operation
- MAC Instruction Set Summary
- Local Memory
- Local Memory Registers
- SRAM Base Address Register (RAMBAR)
- SRAM Initialization
- ROM Base Address Register (ROMBAR)
- Programming ROMBAR for Power Management
- Instruction Cache Overview
- Instruction Cache Block Diagram
- Caching Modes
- Reset
- Instruction Cache Operation as Defined by CACR[CENB,CEIB]
- CACR Field Descriptions
- Access Control Register Format (ACRn)
- Processor/Debug Module Interface
- PSTCLK Timing
- Real-Time Trace Support
- Begin Execution of Taken Branch (PST = 0x5)
- Example JMP Instruction Output on PST/DDATA
- Debug Programming Model
- Address Attribute Trigger Register (AATR)
- Address Breakpoint Registers (ABLR, ABHR)
- Configuration/Status Register (CSR)
- Data Breakpoint/Mask Registers (DBR and DBMR)
- Program Counter Breakpoint Register (PBR)
- Trigger Definition Register (TDR)
- Background Debug Mode (BDM)
- CPU Halt
- BDM Serial Interface Timing
- Receive BDM Packet
- BDM Command Set
- BDM Command Format
- Command Sequence Diagram
- Command Set Descriptions
- WAREG / WDREG Command Format
- Read Memory Location ( READ )
- WRITE Command Format
- WRITE Command Sequence
- NOP Command Format
- Definition of DRc Encoding—Read
- WDMREG BDM Command Format
- Theory of Operation
- Emulator Mode
- Processor Status, DDATA Definition
- PST/DDATA Specification for User-Mode Instructions
- Supervisor Instruction Set
- Recommended BDM Connector
- SIM Block Diagram
- Programming Model
- Module Base Address Register (MBAR)
- System Configuration Register (SCR)
- System Protection Register (SPR)
- Power Management Register (PMR)
- USB and USART Power Down Modes
- Activate Low-Power Register (ALPR)
- Device Identification Register (DIR)
- Watchdog Reset Reference Register (WRRR)
- Watchdog Counter Register (WCR)
- Interrupt Controller Block Diagram
- ColdFire Core
- Interrupt Control Register 1 (ICR1)
- Interrupt Control Register 2 (ICR2)
- Interrupt Source Register (ISR)
- Programmable Interrupt Transition Register (PITR)
- Programmable Interrupt Wakeup Register (PIWR)
- Programmable Interrupt Vector Register (PIVR)
- MCF5272 Interrupt Vector Table
- Boot CS0 Operation
- Chip Select Base Registers (CSBRn)
- Output Read/Write Strobe Levels versus Chip Select EBI Code
- Chip Select Option Registers (CSORn)
- SDRAM Controller Signals
- Pin TSOP SDRAM Pin Definition
- Interface to SDRAM Devices
- Internal Address Multiplexing (16-Bit Data Bus)
- SDRAM Configuration Register (SDCR)
- SDCR Field Descriptions
- SDRAM Timing Register (SDTR)
- Auto Initialization
- Performance
- SDRAM Controller Performance (RCD = 1, RP = 1), 16-Bit Port
- Example Setup Time Violation on SDRAM Data Input during Write
- Timing Refinement with Inverted SDCLK
- Timing Refinement with Effective CAS Latency
- SDRAM Read Accesses
- SDRAM Burst Read, 32-Bit Port, Page Miss, Access = 9-1-1-1
- SDRAM Burst Read, 32-Bit Port, Page Hit, Access = 5-1-1-1
- SDRAM Burst Write, 32-Bit Port, Page Miss, Access = 7-1-1-1
- SDRAM Burst Write, 32-Bit Port, Page Hit, Access = 3-1-1-1
- SDRAM Refresh Cycle
- Enter SDRAM Self-Refresh Mode
- Exit SDRAM Self-Refresh Mode
- DMA Data Transfer Types
- DMA Mode Register (DMR)
- DMA Interrupt Register (DIR)
- DMA Source Address Register (DSAR)
- DMA Destination Address Register (DDAR)
- Ethernet Block Diagram
- Transceiver Connection
- Ethernet Frame Format
- FEC Frame Reception
- CAM Interface
- Ethernet Address Recognition Flowchart
- Hash Table Algorithm
- Ethernet Error-Handling Procedure
- Ethernet Control Register (ECR)
- Interrupt Event Register (EIR)
- Interrupt Mask Register (EIMR)
- Interrupt Vector Status Register (IVSR)
- Receive Descriptor Active Register (RDAR)
- Transmit Descriptor Active Register (TDAR)
- MII Management Frame Register (MMFR)
- MII Speed Control Register (MSCR)
- FIFO Receive Bound Register (FRBR)
- FIFO Receive Start Register (FRSR)
- Transmit FIFO Watermark (TFWR)
- FIFO Transmit Start Register (TFSR)
- Receive Control Register (RCR)
- Maximum Frame Length Register (MFLR)
- Transmit Control Register (TCR)
- RAM Perfect Match Address Low (MALR)
- RAM Perfect Match Address High (MAUR)
- Hash Table High (HTUR)
- Hash Table Low (HTLR)
- Pointer-to-Receive Descriptor Ring (ERDSR)
- Pointer-to-Transmit Descriptor Ring (ETDSR)
- Receive Buffer Size (EMRBR)
- Initialization Sequence
- FEC Initialization
- Receive Buffer Descriptor (RxBD)
- RxBD Field Descriptions
- Transmit Buffer Descriptor (TxBD)
- Differences between MCF5272 FEC and MPC860T FEC
- Introduction
- The USB "Tiered Star" Topology
- USB Module Block Diagram
- Clock Generator
- Endpoint Controllers
- Register Description and Programming Model
- USB Frame Number Register (FNR)
- USB Real-Time Frame Monitor Register (RFMR)
- USB Real-Time Frame Monitor Match Register (RFMMR)
- USB Alternate Settings Register (ASR)
- USB Device Request Data 1 Register (DRR1)
- USB Specification Number Register (SPECR)
- USB Endpoint 0 IN Configuration Register (IEP0CFG)
- USB Endpoint 0 OUT Configuration Register
- USB Endpoint 0 Control Register (EP0CTL)
- USB Endpoint 1-7 Control Register (EPnCTL)
- USB Endpoint 0 Interrupt Mask (EP0IMR and General/Endpoint 0 Interrupt Registers (EP0ISR)
- USB Endpoints 1–7 Interrupt Status Registers (EPnISR)
- USB Endpoint 1-7 Interrupt Mask Registers (EPnIMR)
- USB Endpoint 0-7 Data Registers (EPnDR)
- USB Endpoint 0-7 Data Present Registers (EPnDPR)
- Example USB Configuration Descriptor Structure
- USB Module Access Times
- Software Architecture and Application Notes
- FIFO Configuration
- Control, Bulk, and Interrupt Endpoints
- IN Endpoints
- Endpoint Halt Feature
- Recommended USB Line Interface
- USB Protection Circuit
- PLIC System Diagram
- GCI/IDL Receive Data Flow
- GCI/IDL B-Channel Receive Data Register Demultiplexing
- GCI/IDL B Data Transmit Register Multiplexing
- B-Channel Unencoded and HDLC Encoded Data
- D-Channel HDLC Encoded and Unencoded Data
- D-Channel Contention
- GCI/IDL Loopback Mode
- Periodic Frame Interrupt
- Interrupt Control
- PLIC Internal Timing Signal Routing
- Super Frame Sync Generation
- B1 Receive Data Registers P0B1RR–P3B1RR
- B2 Receive Data Registers P0B2RR – P3B2RR
- B1 Transmit Data Registers P0B1TR–P3B1TR
- D Transmit Data Registers P0DTR–P3DTR
- P0CR–P3CR Field Descriptions
- Loopback Control Register (PLCR)
- P0ICR–P3ICR Field Descriptions
- Periodic Status Registers (P0PSR–P3PSR)
- Aperiodic Status Register (PASR)
- GCI Monitor Channel Receive Registers (P0GMR–P3GMR)
- GCI Monitor Channel Transmit Registers (P0GMT–P3GMT)
- GCI Monitor Channel Transmit Abort Register (PGMTA)
- GCI Monitor Channel Transmit Status Register (PGMTS)
- GCI C/I Channel Receive Registers (P0GCIR–P3GCIR)
- GCI C/I Channel Transmit Registers (P0GCIT–P3GCIT)
- GCI C/I Channel Transmit Status Register (PGCITSR)
- D-Channel Status Register (PDCSR)
- D-Channel Request Registers (PDRQR)
- Sync Delay Registers (P0SDR–P3SDR)
- Clock Select Register (PCSR)
- Application Examples
- Port 1 Configuration Register (P1CR)
- Port 1 Interrupt Configuration Register (P1ICR)
- ISDN SOHO PABX Example
- Standard IDL2 10-Bit Mode
- Standard IDL2 8-Bit Mode
- QSPI Block Diagram
- Interface and Pins
- QSPI RAM
- QSPI RAM Model
- Transmit RAM
- Transfer Delays
- Transfer Length
- QSPI Mode Register (QMR)
- QSPI Clocking and Data Transfer Example
- SPI Modes Timing
- QSPI Wrap Register (QWR)
- QSPI Interrupt Register (QIR)
- QSPI Address Register
- Command RAM Registers (QCR0–QCR15)
- Programming Example
- Timer Block Diagram
- Timer Mode Registers (TMR0–TMR3)
- Timer Reference Registers (TRR0–TRR3)
- Timer Event Registers (TER0–TER3)
- System Integration Module (SIM
- Serial Module Overview
- UART Module Programming Model
- UART Mode Registers 1 (UMR1n)
- UMR1n Field Descriptions
- UART Mode Register 2 (UMR2n)
- UART Status Registers (USRn)
- UART Clock-Select Registers (UCSRn)
- UART Command Registers (UCRn)
- UART Receiver Buffer (URBn)
- UART Transmitter Buffers (UTBn)
- UART Auxiliary Control Registers (UACRn)
- UART Interrupt Status/Mask Registers (UISRn/UIMRn)
- UART Divider Upper Registers (UDUn)
- UART Transmitter FIFO Registers (UTFn)
- UART Receiver FIFO Registers (URFn)
- UART Fractional Precision Divider Control Registers (UFPDn)
- Interrupt Controller
- UART/RS-232 Interface
- Clocking Source Diagram
- External Clock
- Transmitter and Receiver Functional Diagram
- Transmitter Timing
- Receiver Timing
- Transmitter FIFO
- Looping Modes
- Automatic Echo
- Remote Loop-Back
- Multidrop Mode Timing Diagram
- UART Mode Programming Flowchart (Sheet 1 of 5)
- Port Control Registers
- Port A Control Register (PACNT)
- Port B Control Register (PBCNT)
- PBCNT Field Descriptions
- Port B Control Register Function Bits
- Port D Control Register (PDCNT)
- Port D Control Register Function Bits
- Port A Data Direction Register (PADDR)
- Port C Data Direction Register (PCDDR)
- PWM Block Diagram (3 Identical Modules)
- PWM Operation
- PWM Control Registers (PWCRn)
- PWM Width Register (PWWDn)
- MCF5272 Block Diagram with Signal Interfaces
- Signal List
- Signal Name and Description by Pin Number
- SDRAM Controller
- Bus Control Signals
- Read/Write (R/W)
- Transfer Acknowledge (TA/PB5)
- SDRAM Bank Selects (SDBA[1:0])
- General-Purpose I/O (GPIO) Ports
- Receive Serial Data Input (URT0_RxD/PB1)
- USB Transmit Data Negative (USB_TN/PA3)
- Ethernet Module
- Transmit Data (E_TxD0)
- Receive Error (E_RxER/PB14)
- QSPI Synchronous Serial Data Output (QSPI_Dout/WSEL)
- Physical Layer Interface Controller TDM Ports and UART 1
- UART1 CTS (URT1_CTS/QSPI_CS2)
- GCI/IDL Data Out (DOUT1)
- GCI/IDL TDM Ports 2 and 3
- INT4 and Port 3 GCI/IDL Data In (INT4/DIN3)
- Test and Debug Data Out (TDO/DSO)
- Debug Data (DDATA[3:0])
- Power Supply Pins
- Features
- Address Bus (A[22:0])
- Transfer Error Acknowledge (TEA)
- Data Transfer Mechanism
- Internal Operand Representation
- Byte Strobe Operation for 32-Bit Data Bus
- External Bus Interface Types
- Longword Read; EBI = 00; 32-Bit Port; Internal Termination
- Word Write; EBI = 00; 16-/32-Bit Port; Internal Termination
- Longword Write with Address Setup; EBI = 00; 32-Bit Port; Internal Termination
- Longword Write with Address Hold; EBI = 00; 32-Bit Port; Internal Termination
- Longword Read; EBI=11; 32-Bit Port; Internal Termination
- Word Write; EBI=11; 16/32-Bit Port; Internal Termination
- Read with Address Setup; EBI=11; 32-Bit Port; Internal Termination
- Read with Address Hold; EBI=11; 32-Bit Port; Internal Termination
- Burst Data Transfers
- Example of a Misaligned Longword Transfer
- Interrupt Cycles
- Longword Write Access To 32-Bit Port Terminated with TEA Timing
- Bus Arbitration
- Master Reset Timing
- Normal Reset Timing
- Software Watchdog Timer Reset Timing
- Soft Reset Timing
- Test Access Port Block Diagram
- TAP Controller State Machine
- Output Cell (O.Cell) (BC–1)
- Input Cell (I.Cell). Observe only (BC–4)
- Bidirectional Cell (IO.Cell) (BC–6)
- Instruction Register
- Bypass Register
- MCF5272 Pinout (196 MAPBGA)
- MAPBGA Package Dimensions (Case No. 1128A-01)
- Maximum Ratings
- Operating Temperature
- DC Electrical Specifications
- Clock Input Timing Diagram
- Processor Bus Input Timing Specifications
- General Input Timing Requirements
- Processor Bus Output Timing Specifications
- Read/Write SRAM Bus Timing
- SRAM Bus Cycle Terminated by TA
- SRAM Bus Cycle Terminated by TEA
- Reset and Mode Select/HIZ Configuration Timing
- Real-Time Trace AC Timing
- SDRAM Interface Timing Specifications
- SDRAM Signal Timing
- SDRAM Self-Refresh Cycle Timing
- MII Receive Signal Timing Diagram
- MII Transmit Signal Timing Diagram
- MII Async Inputs Timing Diagram
- MII Serial Management Channel Timing Diagram
- Timer Timing
- UART Timing
- IDL Master Timing
- IDL Slave Mode Timing, PLIC Ports 0–3
- IDL Slave Timing
- GCI Slave Mode Timing
- GCI Master Mode Timing
- General-Purpose I/O Port Timing
- USB Interface Timing
- IEEE 1149.1 (JTAG) Timing
- QSPI Timing
- PWM Timing
- A.1 List of Memory Map Tables
- A-2 CPU Space Registers Memory Map
- A-5 Chip Select Register Memory Map
- A-7 QSPI Module Memory Map
- A-10 UART0 Module Memory Map
- A-11 UART1 Module Memory Map
- A-12 SDRAM Controller Memory Map
- A-14 PLIC Module Memory Map
- A-15 Ethernet Module Memory Map
- A-16 USB Module Memory Map
- Physical Layer Interface Controller (PLIC
- Queued Serial Peripheral Interface (QSPI) Module
- Electrical Characteristics
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