MCF5272 ColdFire ® Integrated Microprocessor User’s Manual, Rev. 3x Freescale SemiconductorList of Figures (Continued)Figure PageNumber Title Number16-3 UART Mode Register 2 (UMR2n) ......................................................................................... 16-616-4 UART Status Registers (USRn) ............................................................................................ 16-716-5 UART Clock-Select Registers (UCSRn) ............................................................................... 16-816-6 UART Command Registers (UCRn) ..................................................................................... 16-916-7 UART Receiver Buffer (URBn)............................................................................................ 16-1016-8 UART Transmitter Buffers (UTBn) ...................................................................................... 16-1116-9 UART Input Port Change Registers (UIPCRn) ................................................................... 16-1116-10 UART Auxiliary Control Registers (UACRn) ....................................................................... 16-1216-11 UART Interrupt Status/Mask Registers (UISRn/UIMRn)..................................................... 16-1316-12 UART Divider Upper Registers (UDUn) .............................................................................. 16-1416-13 UART Divider Lower Registers (UDLn)............................................................................... 16-1416-14 UART Autobaud Upper Registers (UABUn)........................................................................ 16-1416-15 UART Autobaud Lower Registers (UABLn) ........................................................................ 16-1416-16 UART Transmitter FIFO Registers (UTFn) ......................................................................... 16-1516-17 UART Receiver FIFO Registers (URFn) ............................................................................. 16-1616-18 UART Fractional Precision Divider Control Registers (UFPDn).......................................... 16-1716-19 UART Input Port Registers (UIPn) ...................................................................................... 16-1716-20 UART Output Port Command Registers (UOP1/UOP0) ..................................................... 16-1816-21 UART Block Diagram Showing External and Internal Interface Signals ............................. 16-1816-22 UART/RS-232 Interface ...................................................................................................... 16-1916-23 Clocking Source Diagram ................................................................................................... 16-2016-24 Transmitter and Receiver Functional Diagram.................................................................... 16-2216-25 Transmitter Timing .............................................................................................................. 16-2316-26 Receiver Timing .................................................................................................................. 16-2416-27 Automatic Echo ................................................................................................................... 16-2716-28 Local Loop-Back ................................................................................................................. 16-2716-29 Remote Loop-Back ............................................................................................................. 16-2816-30 Multidrop Mode Timing Diagram ......................................................................................... 16-2916-31 UART Mode Programming Flowchart (Sheet 1 of 5) .......................................................... 16-3017-1 Port A Control Register (PACNT).......................................................................................... 17-317-2 Port B Control Register (PBCNT).......................................................................................... 17-517-3 Port D Control Register (PDCNT) ......................................................................................... 17-817-4 Port A Data Direction Register (PADDR) ............................................................................ 17-1017-5 Port B Data Direction Register (PBDDR) ............................................................................ 17-1017-6 Port C Data Direction Register (PCDDR)............................................................................ 17-1117-7 Port x Data Register (PADAT, PBDAT, and PCDAT) ......................................................... 17-1118-1 PWM Block Diagram (3 Identical Modules)........................................................................... 18-118-2 PWM Control Registers (PWCRn) ........................................................................................ 18-318-3 PWM Width Register (PWWDn)............................................................................................ 18-418-4 PWM Waveform Examples (PWCRn[EN] = 1)...................................................................... 18-419-1 MCF5272 Block Diagram with Signal Interfaces................................................................... 19-220-1 Internal Operand Representation.......................................................................................... 20-520-2 MCF5272 Interface to Various Port Sizes............................................................................. 20-520-3 Longword Read; EBI = 00; 32-Bit Port; Internal Termination................................................ 20-8
