MCF5272 ColdFire ® Integrated Microprocessor User’s Manual, Rev. 3Freescale Semiconductor 1-1Chapter 1OverviewThis chapter provides an overview of the MCF5272 microprocessor features, including the majorfunctional components.1.1 MCF5272 Key FeaturesA block diagram of the MCF5272 is shown in Figure 1-1. The main features are as follows:• Static Version 2 ColdFire variable-length RISC processor— 32-bit address and data path on-chip— 66-MHz processor core and bus frequency— Sixteen general-purpose 32-bit data and address registers— Multiply-accumulate unit (MAC) for DSP and fast multiply operations• On-chip memories— 4-Kbyte SRAM on CPU internal bus— 16-Kbyte ROM on CPU internal bus— 1-Kbyte instruction cache• Power management— Fully-static operation with processor sleep and whole-chip stop modes— Very rapid response to interrupts from the low-power sleep mode (wake-up feature)— Clock enable/disable for each peripheral when not used— Software-controlled disable of external clock input for virtually zero power consumption(low-power stop mode)• Two universal asynchronous/synchronous receiver transmitters (UARTs)— Full-duplex operation— Based on MC68681 dual-UART (DUART) programming model— Flexible baud rate generator— Modem control signals available (CTS and RTS)— Processor interrupt and wakeup capability— Enhanced Tx, Rx FIFOs, 24 bytes each
