Queued Serial Peripheral Interface (QSPI) ModuleMCF5272 ColdFire ® Integrated Microprocessor User’s Manual, Rev. 314-16 Freescale Semiconductor14.5.8 Programming ExampleThe following steps are necessary to set up the QSPI 12-bit data transfers and a QSPI_CLK of 4.125 MHz.The QSPI RAM is set up for a queue of 16 transfers. All four QSPI_CS signals are used in this example.1. Enable all QSPI_CS pins on the MCF5272. Write PACNT with 0x0080_4000 to enable QSPI_CS1and QSPI_CS3.Write PDCNT with 0x0000_0030 to enable QSPI_CS2.2. Write the QMR with 0xB308 to set up 12-bit data words with the data shifted on the falling clockedge, and a clock frequency of 4.125 MHz (assuming a 66-MHz CLKIN).3. Write QDLYR with the desired delays.4. Write QIR with 0xD00D to enable write collision, abort bus errors, and clear any interrupts.5. Write QAR with 0x0020 to select the first command RAM entry.6. Write QDR with 0x7E00, 0x7E00, 0x7E00, 0x7E00, 0x7D00, 0x7D00, 0x7D00, 0x7D00, 0x7B00,0x7B00, 0x7B00, 0x7B00, 0x7700, 0x7700, 0x7700, and 0x7700 to set up four transfers for eachchip select. The chip selects are active low in this example.7. Write QAR with 0x0000 to select the first transmit RAM entry.8. Write QDR with sixteen 12-bit words of data.9. Write QWR with 0x0F00 to set up a queue beginning at entry 0 and ending at entry 15.10. Set QDLYR[SPE] to enable the transfers.11. Wait until the transfers are complete. QIR[SPIF] is set when the transfers are complete.12. Write QAR with 0x0010 to select the first receive RAM entry.13. Read QDR to get the received data for each transfer.14. Repeat steps 5 through 13 to do another transfer.
