Ethernet ModuleMCF5272 ColdFire ® Integrated Microprocessor User’s Manual, Rev. 3Freescale Semiconductor 11-2511.5.15 Transmit Control Register (TCR)The TCR register, Figure 11-19, controls the operational mode of the transmit blockTable 11-22 describes the TCR fields.31 16Field —Reset 0000_0000_0000_0000R/W Read/Write15 3 2 1 0Field — FDEN HBC GTSReset 0000_0000_0000_0000R/W Read/WriteAddr MBAR + 0x984Figure 11-19. Transmit Control Register (TCR)Table 11-22. TCR Field DescriptionsBits Name Description31–3 — Reserved, should be cleared.2 FDEN Full duplex enable. If set, frames are transmitted independent of carrier sense and collision inputs. Thisbit should only be modified when ETHER_EN is deasserted.1 HBC Heartbeat control. If set, the heartbeat check is performed following end of transmission and the HBbit in the status register is set if the collision input does not assert within the heartbeat window. This bitshould be modified only when ETHER_EN is deasserted.0 GTS Graceful transmit stop. When this bit is set, the MAC stops transmission after any current frame iscomplete and the GRA interrupt in the INTR_EVENT register is asserted. If frame transmission is notcurrently underway, the GRA interrupt is asserted immediately. Once transmission is complete, arestart is accomplished by clearing the GTS bit. The next frame in the transmit FIFO is then transmitted.If an early collision occurs during transmission when GTS = 1, transmission stops after the collision.The frame is transmitted again once GTS is cleared. Note that there may be old frames in the transmitFIFO that are transmitted when GTS is reasserted. To avoid this, deassert ETHER_EN following theGRA interrupt.
