UART ModulesMCF5272 ColdFire ® Integrated Microprocessor User’s Manual, Rev. 316-16 Freescale Semiconductor16.3.14 UART Receiver FIFO Registers (URFn)The URFn registers contain control and status bits for the receiver FIFO. Note that some bits are read only.Table 16-11 describes URFn fields.7 6 5 4 0Field RXS FULL RXBReset 0000_0000R/W R/W R RAddress MBAR + 0x12C (URF0), 0x16C (URF1)Figure 16-17. UART Receiver FIFO Registers (URFn)Table 16-11. URFn Field DescriptionsBits Name Description7–6 RXS Receiver status. When written to, these bits control the meaning of UISRn[RxFIFO].00 Inhibit receiver FIFO status indication in UISRn.01 Receiver FIFO Š 25% full10 Receiver FIFO Š 50% full11 Receiver FIFO Š 75% fullWhen read, these bits indicate the emptiness level of the FIFO.00 Receiver FIFO < 25% full01 Receiver FIFO Š 25% full10 Receiver FIFO Š 50% full11 Receiver FIFO Š 75% full5 FULL Receiver FIFO full.0 Receiver FIFO is not full and can be loaded with a character.1 Receiver FIFO is full. Characters loaded from the receiver when the FIFO is full are lost.This bit is identical to USRn[FFULL].4–0 RXB Receiver buffer data level. Indicates the number of bytes, between 0 and 24, stored in the receiver FIFO.
