MCF5272 ColdFire ® Integrated Microprocessor User’s Manual, Rev. 3Freescale Semiconductor viiList of Figures (Continued)Figure PageNumber Title Number9-4 SDRAM Timing Register (SDTR)............................................................................................ 9-89-5 Example Setup Time Violation on SDRAM Data Input during Write ..................................... 9-129-6 Timing Refinement with Inverted SDCLK.............................................................................. 9-139-7 Timing Refinement with True CAS Latency and Inverted SDCLK ........................................ 9-139-8 Timing Refinement with Effective CAS Latency.................................................................... 9-149-9 SDRAM Burst Read, 32-Bit Port, Page Miss, Access = 9-1-1-1 ........................................... 9-169-10 SDRAM Burst Read, 32-Bit Port, Page Hit, Access = 5-1-1-1 .............................................. 9-179-11 SDRAM Burst Write, 32-Bit Port, Page Miss, Access = 7-1-1-1 ........................................... 9-189-12 SDRAM Burst Write, 32-Bit Port, Page Hit, Access = 3-1-1-1 .............................................. 9-199-13 SDRAM Refresh Cycle.......................................................................................................... 9-209-14 Enter SDRAM Self-Refresh Mode......................................................................................... 9-219-15 Exit SDRAM Self-Refresh Mode ........................................................................................... 9-2210-1 DMA Mode Register (DMR) .................................................................................................. 10-210-2 DMA Interrupt Register (DIR)................................................................................................ 10-410-3 DMA Source Address Register (DSAR)................................................................................ 10-510-4 DMA Destination Address Register (DDAR) ......................................................................... 10-610-5 DMA Byte Count Register (DBCR) ....................................................................................... 10-611-1 Ethernet Block Diagram ........................................................................................................ 11-211-2 Fast Ethernet Module Block Diagram ................................................................................... 11-211-3 Ethernet Frame Format......................................................................................................... 11-411-4 Ethernet Address Recognition Flowchart.............................................................................. 11-711-5 Ethernet Control Register (ECR)......................................................................................... 11-1111-6 Interrupt Event Register (EIR)............................................................................................. 11-1211-7 Interrupt Mask Register (EIMR) ......................................................................................... 11-1311-8 Interrupt Vector Status Register (IVSR) .............................................................................. 11-1411-9 Receive Descriptor Active Register (RDAR) ....................................................................... 11-1511-10 Transmit Descriptor Active Register (TDAR) ...................................................................... 11-1611-11 MII Management Frame Register (MMFR) ......................................................................... 11-1711-12 MII Speed Control Register (MSCR).................................................................................. 11-1811-13 FIFO Receive Bound Register (FRBR) .............................................................................. 11-1911-14 FIFO Receive Start Register (FRSR)................................................................................. 11-2011-15 Transmit FIFO Watermark (TFWR).................................................................................... 11-2111-16 FIFO Transmit Start Register (TFSR) ................................................................................. 11-2211-17 Receive Control Register (RCR) ......................................................................................... 11-2311-18 Maximum Frame Length Register (MFLR).......................................................................... 11-2411-19 Transmit Control Register (TCR) ........................................................................................ 11-2511-20 RAM Perfect Match Address Low (MALR).......................................................................... 11-2611-21 RAM Perfect Match Address High (MAUR) ........................................................................ 11-2711-22 Hash Table High (HTUR) ................................................................................................... 11-2811-23 Hash Table Low (HTLR) .................................................................................................... 11-2911-24 Pointer-to-Receive Descriptor Ring (ERDSR)..................................................................... 11-3011-25 Pointer-to-Transmit Descriptor Ring (ETDSR) .................................................................... 11-3111-26 Receive Buffer Size (EMRBR) ............................................................................................ 11-3211-27 Receive Buffer Descriptor (RxBD) ...................................................................................... 11-35
