Interrupt ControllerMCF5272 ColdFire ® Integrated Microprocessor User’s Manual, Rev. 3Freescale Semiconductor 7-3Chapter 2, “ColdFire Core.” Pending interrupts from external sources (INT[6:1]) can be cleared using theICRs.For an interrupt to be successfully processed, stack RAM must be available. A programmable chip selectis often used for the RAM, in which case, the RAM is not immediately available at startup. Thus, nointerrupts are recognized until PIVR is initialized. The RAM chip select and system stack should be set upbefore this initialization.If more than one interrupt source has the same interrupt priority level (IPL), the interrupt controller daisychains the interrupts with the priority order following the bit placement in the PIWR, with INT1 havingthe highest priority and SWTO having the lowest priority, as shown in Figure 7-8.7.2.1 Interrupt Controller RegistersThis section describes the registers associated with the interrupt controller. Table 7-2 gives thenomenclature used for the interrupt and power management registers.Table 7-2. Interrupt and Power Management Register MnemonicsMnemonic or Portion Thereof DescriptionINT1, INT2, INT3, INT4, INT5, INT6 External interrupt signals 1–6.TMR0, TMR1, TMR2, TMR3 Timers 3–0 from timer moduleUSB0, USB1, USB2, USB3, USB4, USB5,USB6, USB7USB endpoint 0–7UART1, UART2 UART1, UART2 modulesPLIP PLIC 2-KHz periodic interrupt, 2B+D dataPLIA PLIC asynchronous and maintenance channels interruptDMA DMA controller interruptETx Ethernet module transmit data interruptERx Ethernet module receive data interruptENTC Ethernet module non-time-critical interruptQSPI Queued serial peripheral interfaceIPL2, IPL1, IPL0 Interrupt priority level bits 2–0PI Pending interruptPDN Power down enableWK Wakeup enableSWTO Software watchdog timer time out
