Pulse-Width Modulation (PWM) ModuleMCF5272 ColdFire ® Integrated Microprocessor User’s Manual, Rev. 3Freescale Semiconductor 18-318.3.1 PWM Control Register (PWCRn)This register, shown in Figure 18-2, controls the overall operation of the PWM. Unless disabled and thenre-enabled, writing to PWCR while the PWM is running will not alter its operation until the current outputcycle finishes. For example, if the prescale value is changed while the PWM is enabled, the new value willnot take effect until after the counter has “wrapped around”. The PWM must be disabled and thenre-enabled to affect its operation before the end of the current output cycle.Figure 18-2. PWM Control Registers (PWCRn)Table 18-2 gives PWCR field descriptions.7 6 5 4 3 0Field EN FRC1 LVL — CKSELReset 0010_0000R/W Read/WriteAddress MBAR + 0x0C0 (PWCR0); + 0x0C4 (PWCR1); + 0x0C8 (PWCR2)Table 18-2. PWCRn Field DescriptionsBits Name Description7 EN Enable.0 Disables the PWM. While disabled, the PWM is in low-power mode and the prescaler does not count.When the PWM is disabled, the output is forced to the value of PWCRn[LVL].1 Enables the PWM.6 FRC1 Force output high.0 Default reset value. PWM functions normally.1 The PWM drives the output high for the entire counter period. PWCRn[FRC1] has a lower priority thanPWCRn[EN], so setting PWCRn[FRC1] while PWCRn[EN] is cleared has no effect. There are two waysto drive the PWM output high. If PWCRn[EN] is cleared, PWM output immediately assumes the value ofPWCRn[LVL]. If PWCRn[FRC1] is set while PWCRn[EN] is set, the PWM output does not go high untilafter the current output cycle completes.5 LVL Disable level. Determines the PWM output level whenever the PWM is disabled.0 The PWM output is low while disabled.1 The PWM output is high while disabled.4 — Reserved, should be cleared.3–0 CKSL Prescale clock. These bits select the clock frequency divider, that is, the output of the divider chain, asshown below.CKSL[3:0] Divisor0000 10001 20010 4... ...111132768
