Local MemoryMCF5272 ColdFire ® Integrated Microprocessor User’s Manual, Rev. 3Freescale Semiconductor 4-9Cache invalidation can be performed in the two following ways:• Setting CACR[CINVA] forces the entire instruction cache to be marked as invalid. Theinvalidation operation requires 64 cycles because the cache sequences through the entire tag array,clearing a single location each cycle. Any subsequent instruction fetch accesses are postponed untilthe invalidation sequence is complete.• The privileged CPUSHL instruction can invalidate a single cache line. When this instruction isexecuted, the cache entry defined by bits 9–4 of the source address register is invalidated, providedCACR[CDPI] is cleared.These invalidation operations can be initiated from the ColdFire core or the debug module.4.5.2.3 Caching ModesFor every memory reference generated by the processor or debug module, a set of effective attributes isdetermined based on the address and the ACRs. Caching modes determine how the cache handles anaccess. An access can be cacheable or cache-inhibited. For normal accesses, the ACRn[CM] bitcorresponding to the address of the access specifies the caching mode. If an address does not match anACR, the default caching mode is defined by CACR[DCM]. The specific algorithm is as follows:if (address == ACR0-address including mask)effective attributes = ACR0 attributeselse if (address == ACR1-address including mask)effective attributes = ACR1 attributeselse effective attributes = CACR default attributesAddresses matching an ACR can also be write protected using ACR[WP].Reset disables the cache and clears all CACR bits. Reset does not automatically invalidate cache entries;they must be invalidated through software.The ACRs allow CACR defaults to be overridden. In addition, some instructions (for example, CPUSHL)and processor core operations perform accesses that have an implicit caching mode associated with them.The following sections discuss the different caching accesses and their associated cache modes.4.5.2.3.1 Cacheable AccessesIf ACRn[CM] or the default field of the CACR indicates the access is cacheable, a read access is read fromthe cache if matching data is found. Otherwise, the data is read from memory and the cache is updated.When a line is being read from memory, the longword in the line that contains the core-requested data isloaded first and the requested data is given immediately to the processor, without waiting for the threeremaining longwords to reach the cache.4.5.2.3.2 Cache-Inhibited AccessesMemory regions can be designated as cache-inhibited, which is useful for memory containing targets suchas I/O devices and shared data structures in multiprocessing systems. Do not cache memory-mappedregisters (for example, registers shown with an MBAR offset). If the corresponding ACRn[CM] orCACR[DCM] indicates cache-inhibited the access is cache-inhibited. The caching operation is identicalfor both cache-inhibited modes, which differ only regarding recovery from an external bus error.
