ColdFire CoreMCF5272 ColdFire ® Integrated Microprocessor User’s Manual, Rev. 3Freescale Semiconductor 2-27ColdFire processors inhibit sampling for interrupts during the first instruction of all exception handlers.This allows any handler to effectively disable interrupts, if necessary, by raising the interrupt mask levelcontained in the status register.2.8.1 Exception Stack Frame DefinitionThe exception stack frame is shown in Figure 2-10. The first longword of the exception stack framecontains the 16-bit format/vector word (F/V) and the 16-bit status register. The second longword containsthe 32-bit program counter address.The 16-bit format/vector word contains three unique fields:• Format field—This 4-bit field at the top of the system stack is always written with a value of{4,5,6,7} by the processor indicating a 2-longword frame format. See Table 2-19. This fieldrecords any longword misalignment of the stack pointer that may have existed when the exceptionoccurred.• Fault status field—The 4-bit field, FS[3–0], at the top of the system stack is defined for access andaddress errors along with interrupted debug service routines. See Table 2-20.61 0F4 Fault Unsupported instruction62–63 0F8–0FC — Reserved64–255 100–3FC Next User-defined interrupts1 The term ‘fault’ refers to the PC of the instruction that caused the exception. The term ‘next’ refers to the PCof the instruction that immediately follows the instruction that caused the fault.31 28 27 26 25 18 17 16 15 0A7→ Format FS[3–2] Vector[7–0] FS[1–0] Status Register+ 0x04 Program Counter [31–0]Figure 2-10. Exception Stack Frame FormTable 2-19. Format Field EncodingOriginal A7 at Time ofException, Bits 1–0A7 at First Instruction ofHandlerFormat Field Bits31–2800 Original A[7–8] 010001 Original A[7–9] 010110 Original A[7–10] 011011 Original A[7–11] 0111Table 2-18. Exception Vector Assignments (continued)VectorNumbersVector Offset(Hex)StackedProgram Counter 1 Assignment
