Signal DescriptionsMCF5272 ColdFire ® Integrated Microprocessor User’s Manual, Rev. 319-28 Freescale Semiconductor19.13.2 Transmit Data (E_TxD0)E_TxD0 is the serial output Ethernet data and is only valid during the assertion of Tx_EN. This signal isused for 10-Mbps Ethernet data. This signal is also used for MII mode data in conjunction withE_TxD[3:1].19.13.3 Collision (E_COL)The E_COL input is asserted upon detection of a collision and remains asserted while the collision persists.This signal is not defined for full-duplex mode.19.13.4 Receive Data Valid (E_RxDV)Asserting the receive data valid (E_RxDV) input indicates that the PHY has valid nibbles present on theMII. E_RxDV should remain asserted from the first recovered nibble of the frame through to the lastnibble. Assertion of E_RxDV must start no later than the SFD and exclude any EOF.19.13.5 Receive Clock (E_RxCLK)The receive clock (E_RxCLK) input provides a timing reference for E_RxDV, E_RxD[3:0], and E_RxER.19.13.6 Receive Data (E_RxD0)E_RxD0 is the Ethernet input data transferred from the PHY to the media-access controller when E_RxDVis asserted. This signal is used for 10-Mbps Ethernet data. This signal is also used for MII mode Ethernetdata in conjunction with E_RxD[3:1].19.13.7 Transmit Enable (E_TxEN)The transmit enable (E_TxEN) output indicates when valid nibbles are present on the MII. This signal isasserted with the first nibble of a preamble and is negated before the first E_TxCLK following the finalnibble of the frame.19.13.8 Transmit Data (E_TxD[3:1]/PB[10:8])Ethernet mode: These pins contain the serial output Ethernet data and are valid only during assertion ofE_TxEN in MII mode.Port B mode: These pins can also be configured as I/O pins PB[10:8].19.13.9 Receive Data (E_RxD[3:1]/PB[13:11])Ethernet mode: These pins contain the Ethernet input data transferred from the PHY to the media-accesscontroller when E_RxDV is asserted in MII mode operation.Port B mode: These pins can also be configured as I/O pins PB[13:11].
