Local MemoryMCF5272 ColdFire ® Integrated Microprocessor User’s Manual, Rev. 34-4 Freescale SemiconductorThe mapping of a given access into the SRAM uses the following algorithm to determine if the access hitsin the memory:if (RAMBAR[0] = 1)if (requested address[31:12] = RAMBAR[31:12])if (address space mask of the requested type = 0)Access is mapped to the SRAM moduleif (access = read)Read the SRAM and return the dataif (access = write)if (RAMBAR[8] = 0)Write the data into the SRAMelse Signal a write-protect access error4.3.2.2 SRAM InitializationAfter a hardware reset, the contents of the SRAM module are undefined. The valid bit of RAMBAR iscleared, disabling the module. If the SRAM needs to be initialized with instructions or data, the followingsteps should be performed:1. Load RAMBAR, mapping the SRAM module to the desired location.2. Read the source data and write it to the SRAM. Various instructions support this function,including memory-to-memory MOVE instructions and the MOVEM opcode. The MOVEMinstruction is optimized to generate line-sized burst fetches on 0-modulo-16 addresses, so thisopcode generally provides the best performance.3. After data is loaded into the SRAM, it may be appropriate to load a revised value into RAMBARwith new write-protect and address space mask attributes. These attributes consist of thewrite-protect and address-space mask fields.The ColdFire processor or an external BDM emulator using the debug module can perform thisinitialization.4.3.2.3 Programming RAMBAR for Power ManagementDepending on the configuration defined by RAMBAR, instruction fetch accesses can be sent to the SRAMmodule, ROM module, and instruction cache simultaneously. If the access is mapped to the SRAMmodule, it sources the read data, discarding the instruction cache access. If the SRAM is used only for dataoperands, setting RAMBAR[SC,UC] lowers power dissipation by disabling the SRAM during allinstruction fetches. Additionally, if the SRAM holds only instructions, setting RAMBAR[SD,UD] reducespower dissipation.Consider the examples on Table 4-3 of typical RAMBAR settings:Table 4-3. Examples of Typical RAMBAR SettingsData Contained in SRAM RAMBAR[7–0]Instructions only 0x2BData only 0x35Both instructions and data 0x21
