SDRAM ControllerMCF5272 ColdFire ® Integrated Microprocessor User’s Manual, Rev. 39-10 Freescale SemiconductorTo wake up the SDRAMs, SDCR[GSL] must be cleared. SDCR[SLEEP] remains set while the SDRAMis exiting sleep mode and is cleared when the SDRAM completes the correct sequence to exit sleep mode.9.8 PerformanceThe maximum performance of the SDRAM controller is determined by the required number of cycles forpage activation and precharge. The read access is influenced by the CAS latency. All SDRAM accessesare in page mode. The following table shows the number of required cycles including all dead cycles foreach type of read/write SDRAM access. It assumes default timing configuration using an at leastPC100-compliant SDRAM device at 66 MHz. Page miss latency includes the cycles to precharge the lastopen page and activate the new page before the read/write access. There are no precharge cycles when anaddress hits an open page.In Table 9-9, the timing configuration is RTP = 61, RC = negligible, RCD = 0 (or 1), RP = 1 (or 0), andCLT = 1.In Table 9-10, the timing configuration is RTP = 61, RC = negligible, RCD = 0, RP = 0, and CLT = 1.Table 9-9. SDRAM Controller Performance, 32-Bit Port, (RCD = 0, RP = 1) or (RCD = 1, RP = 0)SDRAM AccessNumber of System Clock CyclesREG = 0, INV = 0 REG = 1, INV = 0Single-beat read Page miss 8 9Page hit 5 6Single-beat write Page miss 6 6Page hit 3 3Burst read Page miss 8-1-1-1 = 11 9-1-1-1 = 12Page hit 5-1-1-1 = 8 6-1-1-1 = 9Burst write Page miss 6-1-1-1 = 9 6-1-1-1 = 9Page hit 3-1-1-1 = 6 3-1-1-1 = 6Table 9-10. SDRAM Controller Performance, 32–Bit Port, (RCD = 0, RP = 0)SDRAM AccessNumber of System Clock CyclesREG = 0, INV = 0 REG = 1, INV = 0Single-beat read Page miss 7 8Page hit 5 6Single-beat write Page miss 5 5Page hit 3 3Burst read Page miss 7-1-1-1 = 10 8-1-1-1 = 11Page hit 5-1-1-1 = 8 6-1-1-1 = 9Burst write Page miss 5-1-1-1 = 8 5-1-1-1 = 8Page hit 3-1-1-1 = 6 3-1-1-1 = 6
