Debug SupportMCF5272 ColdFire ® Integrated Microprocessor User’s Manual, Rev. 35-40 Freescale Semiconductor5.7.2 Supervisor Instruction SetThe supervisor instruction set has complete access to the user mode instructions plus the opcodes shownbelow. The PST/DDATA specification for these opcodes is shown in Table 5-23.The move-to-SR and RTE instructions include an optional PST = 0x3 value, indicating an entry into usermode. Additionally, if the execution of a RTE instruction returns the processor to emulator mode, amultiple-cycle status of 0xD is signaled.Similar to the exception processing mode, the stopped state (PST = 0xE) and the halted state (PST = 0xF)display this status throughout the entire time the ColdFire processor is in the given mode.Table 5-23. PST/DDATA Specification for Supervisor-Mode InstructionsInstruction Operand Syntax PST/DDATAcpushl PST = 0x1halt PST = 0x1,PST = 0xFmove.w SR,Dx PST = 0x1move.w {Dy,#imm},SR PST = 0x1, {PST = 0x3}movec Ry,Rc PST = 0x1rte PST = 0x7, {PST = 0xB, DD = source operand}, {PST = 3},{ PST =0xB, DD =sourceoperand},PST = 0x5, {[PST = 0x9AB], DD = target address}stop #imm PST = 0x1,PST = 0xEwdebug y PST = 0x1, {PST = 0xB, DD = source, PST = 0xB, DD = source}
