MCF5272 ColdFire ® Integrated Microprocessor User’s Manual, Rev. 3Freescale Semiconductor xvTable of Contents (Continued)Paragraph PageNumber Title NumberChapter 4Local Memory4.1 Interactions between Local Memory Modules .............................................................................. 4-14.2 Local Memory Registers ................................................................................................................ 4-24.3 SRAM Overview ........................................................................................................................... 4-24.3.1 SRAM Operation ................................................................................................................ 4-24.3.2 SRAM Programming Model .............................................................................................. 4-24.3.2.1 SRAM Base Address Register (RAMBAR) ......................................................... 4-34.3.2.2 SRAM Initialization ............................................................................................. 4-44.3.2.3 Programming RAMBAR for Power Management ............................................... 4-44.4 ROM Overview .............................................................................................................................. 4-54.4.1 ROM Operation .................................................................................................................. 4-54.4.2 ROM Programming Model ................................................................................................. 4-54.4.2.1 ROM Base Address Register (ROMBAR) ........................................................... 4-54.4.2.2 Programming ROMBAR for Power Management ............................................... 4-64.5 Instruction Cache Overview .......................................................................................................... 4-74.5.1 Instruction Cache Physical Organization ........................................................................... 4-74.5.2 Instruction Cache Operation ............................................................................................... 4-84.5.2.1 Interaction with Other Modules ............................................................................ 4-84.5.2.2 Cache Coherency and Invalidation ....................................................................... 4-84.5.2.3 Caching Modes ..................................................................................................... 4-94.5.2.3.1 Cacheable Accesses ..................................................................................... 4-94.5.2.3.2 Cache-Inhibited Accesses ............................................................................ 4-94.5.2.4 Reset ................................................................................................................... 4-104.5.2.5 Cache Miss Fetch Algorithm/Line Fills ............................................................. 4-104.5.3 Instruction Cache Programming Model ........................................................................... 4-124.5.3.1 Cache Control Register (CACR) ........................................................................ 4-124.5.3.2 Access Control Registers (ACR0 and ACR1) .................................................... 4-14Chapter 5Debug Support5.1 Overview ........................................................................................................................................ 5-15.2 Signal Description .......................................................................................................................... 5-25.3 Real-Time Trace Support ............................................................................................................... 5-35.3.1 Begin Execution of Taken Branch (PST = 0x5) ................................................................. 5-45.4 Programming Model ...................................................................................................................... 5-55.4.1 Revision A Shared Debug Resources ................................................................................. 5-75.4.2 Address Attribute Trigger Register (AATR) ...................................................................... 5-75.4.3 Address Breakpoint Registers (ABLR, ABHR) ................................................................. 5-95.4.4 Configuration/Status Register (CSR) ............................................................................... 5-10
