SDRAM ControllerMCF5272 ColdFire ® Integrated Microprocessor User’s Manual, Rev. 39-8 Freescale Semiconductor9.5.2 SDRAM Timing Register (SDTR)The SDTR is used to configure SDRAM controller refresh counters for the type of SDRAM devices usedand the number of clocks required for each type of SDRAM access. The reset value is 0x2115. For lowerCPU clock frequencies, precharge and activate times can be reduced to eliminate up to 2 clock cycles fromthe read and write accesses. Consult the data sheets of the SDRAMs being considered.Table 9-8 describes SDTR fields.15 10 9 8 7 6 5 4 3 2 1 0Write RTP RC — RP RCD CLTReset 0010_00 01 00 01 01 01R/W R/WAddr MBAR + 0x0186Figure 9-4. SDRAM Timing Register (SDTR)Table 9-8. SDTR Field DescriptionsBits Name Description15–10 RTP Refresh timer prescaler. Determines the number of clock cycles x 16 between refreshes. The following tabledescribes different recommended prescaler settings for different clock frequencies including a margin of 1.2μS. Recommended values are as follows:RTP 15.6 μs = 1/f*RTP*16 System Clock111101 61 66 MHz101011 43 48 MHz011101 29 33 MHz010110 22 25 MHz000100 4 5 MHz (emulator)9–8 RC Refresh count. Indicates the number of clock cycles spent in refresh state (RC + 5). Refresh occurs duringthe first of these clock cycles; the rest of the time is the delay that must occur before the SDRAM is readyto do anything else.00 5 cycles01 6 cycles (default)10 7 cycles11 8 cycles7–6 — Reserved, should be cleared.5–4 RP Precharge time. Specifies number of clock cycles taken for a precharge (RP + 1).00 1 cycle01 2 cycles (default)10 3 cycles11 4 cycles
