Local MemoryMCF5272 ColdFire ® Integrated Microprocessor User’s Manual, Rev. 3Freescale Semiconductor 4-34.3.2.1 SRAM Base Address Register (RAMBAR)RAMBAR determines the base address location of the internal SRAM module, as well as the definition ofthe types of accesses allowed for it.• RAMBAR is a 32-bit write-only supervisor control register. It is accessed in the CPU address spacevia the MOVEC instruction with an Rc encoding of 0xC04. RAMBAR can be read or written inbackground debug mode (BDM). At system reset, the V bit is cleared and the remaining bits areuninitialized. To access the SRAM module, RAMBAR must be written with the appropriate baseaddress after system reset.• The SRAM base address register (RAMBAR) can be accessed only in supervisor mode using theMOVEC instruction with an Rc value of 0xC04.Figure 4-1. SRAM Base Address Register (RAMBAR)RAMBAR fields are described in Table 4-2.31 12 11 9 8 7 6 5 4 3 2 1 0Field BA — WP — C/I SC SD UC UD VReset — 0R/W W for CPU; R/W for debugAddress CPU space + 0xC04Table 4-2. RAMBAR Field DescriptionBits Name Description31–12 BA Base address. SRAM module base address. The SRAM module occupies a 4-Kbyte space definedby BA. SRAM can reside on any 4-Kbyte boundary in the 4-Gbyte address space.11–9 — Reserved, should be cleared.8 WP Write protect. Controls read/write properties of the SRAM.0 Allows read and write accesses to the SRAM module.1 Allows only read accesses to the SRAM module. Any attempted write reference generates anaccess error exception to the ColdFire processor core.7–6 — Reserved, should be cleared.5–1 C/I,SC,SD,UC, UDAddress space masks (ASn). These fields allow certain types of accesses to be masked, or inhibitedfrom accessing the SRAM module. These bits are useful for power management as described inSection 4.3.2.3, “Programming RAMBAR for Power Management.” In particular, C/I is typically set.The address space mask bits are follows:C/I = CPU space/interrupt acknowledge cycle mask. Note that C/I must be set if BA = 0.SC = Supervisor code address space maskSD = Supervisor data address space maskUC = User code address space maskUD = User data address space maskFor each ASn bit:0 An access to the SRAM module can occur for this address space1 Disable this address space from the SRAM module. References to this address space cannotaccess the SRAM module and are processed like other non-SRAM references.0 V Valid. Enables/disables the SRAM module. V is cleared at reset.0 RAMBAR contents are not valid.1 RAMBAR contents are valid.
