Ethernet ModuleMCF5272 ColdFire ® Integrated Microprocessor User’s Manual, Rev. 3Freescale Semiconductor 11-19The MII_SPEED field must be programmed with a value to provide an E_MDC frequency of less than orequal to 2.5 MHz to be compliant with the IEEE MII specification. The MII_SPEED must be set to anon-zero value in order to source a read or write management frame. After the management frame iscomplete, the MSCR register may optionally be set to zero to turn off the E_MDC. The E_MDC generatedwill have a 50% duty cycle except when MII_SPEED is changed during operation. Change will take effectfollowing either a rising or falling edge of E_MDC.If the system clock is 50 MHz, programming this register to 0x0000_000A results in an E_MDC frequencyof 25 MHz * 1/10 = 2.5 MHz. Table 11-15 shows optimum values for MII_SPEED as a function of systemclock frequency.11.5.9 FIFO Receive Bound Register (FRBR)FRBR is a read-only register used to determine the upper address boundary of the FIFO RAM. Drivers canuse this value, along with the registers FRSR and TFSR, to appropriately divide the available FIFO RAMbetween the transmit and receive data paths. The value in this register must be added to MBAR + 0x800to determine the absolute address.Table 11-16 describes the FRBR fields.Table 11-15. Programming Examples for MSCR RegisterSystem Clock Frequency [MII_SPEED] E_MDC frequency25 MHz 0x3 2.08 MHz33 MHz 0x4 2.06 MHz50 MHz 0x5 2.5 MHz66 MHz 0x7 2.36 MHz31 16Field —Reset 0000_0000_0000_0000R/W Read only15 11 10 2 1 0Field — R_BOUND —Reset 0000_0 110_0000_00 00R/W Read onlyAddr MBAR + 0x884Figure 11-13. FIFO Receive Bound Register (FRBR)Table 11-16. FRBR Field DescriptionsBits Name Description31–11 — Reserved, should be cleared.10–2 R_BOUND End of FIFO RAM. This field contains the ending address of the FIFO RAM, exclusive.1–0 — Reserved, should be cleared.
