Queued Serial Peripheral Interface (QSPI) ModuleMCF5272 ColdFire ® Integrated Microprocessor User’s Manual, Rev. 314-10 Freescale SemiconductorFigure 14-4 shows an example of a QSPI clocking and data transfer.Figure 14-4. QSPI Clocking and Data Transfer Example13–10 BITS Transfer size. Determines the number of bits to be transferred for each entry in the queue.Value Bits per transfer0000 160001– 0111 Reserved1000 81001 91010 101011 111100 121101 131110 141111 159 CPOL Clock polarity. Defines the clock polarity of SCK.0 The inactive state value of QSPI_CLK is logic level 0.1 The inactive state value of QSPI_CLK is logic level 1.8 CPHA Clock phase. Defines the QSPI_CLK clock-phase.0 Data captured on the leading edge of QSPI_CLK and changed on the following edge of QSPI_CLK.1 Data changed on the leading edge of QSPI_CLK and captured on the following edge of QSPI_CLK.7–0 BAUD Baud rate divider. The baud rate is selected by writing 0, or a value in the range 2–255. 1 is not a validvalue. A value of zero disables the QSPI. The desired QSPI_CLK baud rate is related to CLKIN andQMR[BAUD] by the following expression:QMR[BAUD] = SystemClock / [2 × (desired QSPI_CLK baud rate)]Table 14-3. QMR Field Descriptions (continued)Bits Name DescriptionQSPI_CLKQSPI_DoutQSPI_DinQSPI_CSA BQMR[CPOL] = 0QMR[CPHA] = 1QCR[CONT] = 0Chip selects are active lowA = QDLYR[QCD]B = QDLYR[DTL]15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 015 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0msb
