OverviewMCF5272 ColdFire ® Integrated Microprocessor User’s Manual, Rev. 31-6 Freescale Semiconductor1.2.2.4 Power ManagementThe sleep and stop power management modes reduce power consumption by allowing software to shutdown the core, peripherals, or the whole device during inactive periods. To reduce power consumptionfurther, software can individually disable internal clocks to the on-chip peripheral modules. Thepower-saving modes are described as follows:• Sleep mode uses interrupt control logic to allow any interrupt condition to wake the processor. Asthe MCF5272 is fully static, sleep mode is simply the disabling of the core’s clock after the currentinstruction completes. An interrupt from any internal or external source causes on-chip powermanagement logic to reenable the core’s clock; execution resumes with the next instruction. Thisallows rapid return from power-down state as compared to a dynamic implementation that mustperform power-on reset processing before software can handle the interrupt request. If interruptsare enabled at the appropriate priority level, program control passes to the relevant interrupt serviceroutine.• Stop mode is entered by the disabling of the external clock input and is achieved by software settinga bit in a control register. Program execution stops after the current instruction. In stop mode,neither the core nor peripherals are active. The MCF5272 consumes very little power in this mode.To resume normal operation, the external interrupts cause the power management logic tore-enable the external clock input. The MCF5272 resumes program execution from where itentered stop mode (if no interrupt are pending), or starts interrupt exception processing if interruptsare pending.1.2.2.5 Parallel Input/Output PortsThe MCF5272 has up to three 16-bit general-purpose parallel ports, each line of which can be programmedas either an input or output. Some port lines have dedicated pins and others are shared with other MCF5272functions. Some outputs have high drive current capability.1.2.2.6 Interrupt InputsThe MCF5272 has flexible latched interrupt inputs each of which can generate a separate, maskableinterrupt with programmable interrupt priority level and triggering edge (falling or rising). Each interrupthas its own interrupt vector.1.2.3 UART ModuleThe MCF5272 has two full-duplex UART modules with an on-chip baud rate generator providing bothstandard and non-standard baud rates up to 5 Mbps. The module is functionally equivalent to the MC68681DUART with enhanced features including 24-byte Tx and Rx FIFOs. Data formats can be 5, 6, 7, or 8 bitswith even, odd, or no parity and up to 2 stop bits in 1/16-bit increments. Receive and transmit FIFOsminimize CPU service calls. A wide variety of error detection and maskable interrupt capability isprovided.Using a programmable prescaler or an external source, the MCF5272 system clock supports various baudrates. Modem support is provided with request-to-send (RTS) and clear-to-send (CTS) lines availableexternally. Full-duplex autoecho loopback, local loopback, and remote loopback modes can be selected.
