System Integration Module (SIM)MCF5272 ColdFire ® Integrated Microprocessor User’s Manual, Rev. 3Freescale Semiconductor 6-76.2.5 Power Management Register (PMR)The power management register (PMR), Figure 6-5, is used to control the various low-power optionsincluding low-power sleep, low-power stop, and powering down individual on-chip modules.Table 6-5 describes PMR fields.11, 3 HWT,HWTENHardware watchdog timeout. This bit is set when the hardware watchdog timer has reached itsprogrammed timeout value. If HWTEN is also set, the bus cycle is terminated with an access errorexception.10, 2 RPV,RPVENRead protect violation. This bit is set when a read access is attempted to an area for which the chip selectis set to write only. If RPVEN is also set, the bus cycle is terminated with an access error exception.9, 1 EXT,EXTENExternal transfer error. This bit is set when an external transfer error is reported to the SIM on TEA. IfEXTEN is also set, the bus cycle is terminated with an access error exception.8, 0 SUV,SUVENSupervisor/user violation. This bit is set when a user mode access is attempted to an area for which thechip select is set to supervisor only. If SUVEN is also set, the bus cycle is terminated with an access errorexception.31 30 27 26 25 24Field BDMPDN — ENETPDN PLIPDN DRAMPDNReset 0000_0000R/W R/W, Supervisor mode only23 22 21 20 19 18 17 16Field DMAPDN PWMPDN QSPIPDN TIMERPDN GPIOPDN USBPDN UART1PDN UART0PDNReset 0000_0000R/W R/W, Supervisor mode only15 11 10 9 8Field — USBWK UART1WK UART0WKReset 0000_0000R/W R/W, Supervisor mode only7 6 5 4 3 0Field — MOS SLPEN —Reset 0000_0000R/W R/W, Supervisor mode onlyAddress MBAR+0x008Figure 6-5. Power Management Register (PMR)Table 6-4. SPR Field Descriptions (continued)Bits Fields Description
