MCF5272 ColdFire ® Integrated Microprocessor User’s Manual, Rev. 3Freescale Semiconductor xiiiTable of ContentsParagraph PageNumber Title NumberChapter 1Overview1.1 MCF5272 Key Features ................................................................................................................. 1-11.2 MCF5272 Architecture .................................................................................................................. 1-41.2.1 Version 2 ColdFire Core ..................................................................................................... 1-41.2.2 System Integration Module (SIM) ...................................................................................... 1-51.2.2.1 External Bus Interface .......................................................................................... 1-51.2.2.2 Chip Select and Wait State Generation ................................................................. 1-51.2.2.3 System Configuration and Protection ................................................................... 1-51.2.2.4 Power Management .............................................................................................. 1-61.2.2.5 Parallel Input/Output Ports ................................................................................... 1-61.2.2.6 Interrupt Inputs ..................................................................................................... 1-61.2.3 UART Module .................................................................................................................... 1-61.2.4 Timer Module ..................................................................................................................... 1-71.2.5 Test Access Port ................................................................................................................. 1-71.3 System Design .............................................................................................................................. 1-71.3.1 System Bus Configuration .................................................................................................. 1-71.4 MCF5272-Specific Features .......................................................................................................... 1-71.4.1 Physical Layer Interface Controller (PLIC) ....................................................................... 1-71.4.2 Pulse-Width Modulation (PWM) Unit ............................................................................... 1-81.4.3 Queued Serial Peripheral Interface (QSPI) ........................................................................ 1-81.4.4 Universal Serial Bus (USB) Module .................................................................................. 1-8Chapter 2ColdFire Core2.1 Features and Enhancements ........................................................................................................... 2-12.1.1 Decoupled Pipelines ........................................................................................................... 2-12.1.1.1 Instruction Fetch Pipeline (IFP) ............................................................................ 2-22.1.1.2 Operand Execution Pipeline (OEP) ...................................................................... 2-22.1.1.2.1 Illegal Opcode Handling .............................................................................. 2-32.1.1.2.2 Hardware Multiply/Accumulate (MAC) Unit.............................................. 2-32.1.1.2.3 Hardware Divide Unit.................................................................................. 2-42.1.2 Debug Module Enhancements ............................................................................................ 2-42.2 Programming Model ...................................................................................................................... 2-42.2.1 User Programming Model .................................................................................................. 2-42.2.1.1 Data Registers (D0–D7) ....................................................................................... 2-5
