System Integration Module (SIM)MCF5272 ColdFire ® Integrated Microprocessor User’s Manual, Rev. 3Freescale Semiconductor 6-116.2.7 Device Identification Register (DIR)The DIR, Figure 6-7, contains a value representing the identification mark for the MCF5272 device. Thisregister contains the same value as the JTAG IDCODE register. The version number field will change if anew revision of the MCF5272 is created.Figure 6-7. Device Identification Register (DIR)Table 6-8 describes the DIR fields.6.2.8 Software Watchdog TimerThe software watchdog timer prevents system lockup should the software become trapped in loops withno controlled exit. The software watchdog timer can be enabled or disabled through WRRR[EN]. Ifenabled, the watchdog timer requires the periodic execution of a software watchdog servicing sequence.If this periodic servicing action does not occur, the timer counts until it reaches the reset timeout value,resulting in a hardware reset with RSTO driven low for 16 clocks. SCR[RSTSRC] is updated to indicatethat the software watchdog caused the reset.General purpose timers Yes, interrupt No NoEthernet Yes, interrupt No NoDMA controller Yes, interrupt No NoPWM No No NoHardware watchdog timer No No NoSoftware watchdog timer Yes, interrupt No No31 28 27 22 21 12 11 1 0Field VersionNumberDesign Center Device Number JEDEC ID —Value 0010forK75N0100_01 00_0000_0011 0000_0001_110 1R/W Read onlyAddress MBAR+0x010Table 6-8. DIR Field DescriptionsBits Description31–28 Version number. Indicates the revision number of the MCF5272.27–22 Design center. Indicates the ColdFire design center21–12 Device number. Indicates an MCF527211–1 Indicates the reduced JEDEC ID for Freescale. Joint Electron Device Engineering Council (JEDEC) Publication106-A and Chapter 11 of the IEEE Standard 1149.1 give more information on this field.Table 6-7. Exiting Sleep and Stop Modes (continued)Interrupt Source Exit Sleep Exit Stop USB Wake-on-Ring
