Bus OperationMCF5272 ColdFire ® Integrated Microprocessor User’s Manual, Rev. 3Freescale Semiconductor 20-3TA must always be negated before it can be recognized as asserted again. If held asserted into the followingbus cycle, it has no effect and does not terminate the bus cycle.NOTEFor the MCF5272 to accept the transfer as successful with a transferacknowledge, TEA must be negated throughout the transfer.TA is not used for termination during SDRAM accesses.20.2.5 Transfer Error Acknowledge (TEA)An external slave asserts this active-low input signal to abort a transfer. The assertion of TEA immediatelyaborts the bus cycle. The assertion of TEA has precedence over the assertion of TA.The MCF5272 edge-detects and retimes the TEA input. TEA is an asynchronous input signal.The TEA signal function is available after reset. If TEA is not used, a pullup resistor or gating logic mustbe used to ensure the input is inactive. TEA should be negated on the negating edge of the active chipselect. TEA must always be negated before it can be recognized as asserted again. If held asserted into thefollowing bus cycle, it has no effect and does not abort the bus cycle.TEA has no affect during SDRAM accesses.20.3 Bus Exception: Double Bus FaultWhen a bus error or an address error occurs during the exception processing sequence for a previous buserror, a previous address error, or a reset exception, the bus or address error causes a double bus fault. Ifthe MCF5272 experiences a double bus fault, it enters the halted state. To exit the halt state, reset theMCF5272.20.4 Bus CharacteristicsThe MCF5272 uses the address bus (A[22:0]) to specify the location for a data transfer and the data bus(D[31:0] or D[31:16]) to transfer the data. Control signals indicate the direction of the transfer. Theselected device or the number of wait states programmed in the chip select base registers (CSBRs), thechip select option registers (CSORs), the SDRAM configuration and SDRAM timing registers (SDCR,SDTR) control the length of the cycle.The MCF5272 clock is distributed internally to provide logic timing. All SRAM and ROM mode bussignals should be considered as asynchronous with respect to CLKIN. SDCR[INV] allows the SDRAMcontrol signals to be asserted and negated synchronous with the rising or falling edge of SDCLK. TheSDRAM control signals are BS[3:0], SDBA[1:0], RAS0, CAS0, SDWE, A10_PRECHG, SDCLKE, andCS7/SDCS.The asynchronous INT[6:1] signals are internally synchronized to resolve the input to a valid level beforebeing used.
