SDRAM ControllerMCF5272 ColdFire ® Integrated Microprocessor User’s Manual, Rev. 39-14 Freescale SemiconductorSelecting a system clock frequency low enough that the SDCLK-to-CLK delay is long compared to theSDRAM read access time reduces effective CAS latency by 1 cycle.Figure 9-8. Timing Refinement with Effective CAS LatencyNOTEWhen reduced effective CAS latency is used, the SDRAM is stillprogrammed with true CAS latency. The SDRAM controller state machinemust be reprogrammed for the reduced CAS latency. SDRAM initializationsoftware programs the CAS latency of 2 and transfers it into the SDRAMmode register. After SDRAM initialization is confirmed, initializationsoftware should change SDTR[CLT] to CAS latency 1 but should notreinitialize the SDRAM. The SDRAM controller state machine now runswith CAS latency 1 and SDRAMs run with CAS latency 2, which increasesbandwidth on the SDRAM bank and improves performance.9.10 SDRAM InterfaceSetting CSBRn[EBI] to 0b01 enables chip select CS7 for use with one physical bank of SDRAM. In thiscase, CS7 becomes SDCS. The SDRAM memory array may have a 32- or 16-bit data bus width; an 8-bitwidth is not supported. An array may consist of SDRAM devices with 8, 16, or 32 bits data bus width.Each SDRAM device can have from 16–256 Mbits.The interface to the SDRAM devices is glueless. The following control signals are dedicated to SDRAM:SDCS, SDWE, A10_PRECHG, SDCLK, SDCLKE, RAS0, CAS0, and SDBA[1:0].If SDRAM EBI mode is used, CSOR7[WAITST] should be programmed for 0x1F to ensure that theinternal bus cycle termination signal is sourced from the SDRAM controller and not the chip selectmodule.Shifted delay of SDCLKDelay SDCLK to CLKSDRAM read access timeT SDCLK_to_CLK - T acc > 0 => effective CAS latency reduced by 1CASL = 1SDCLKDataInternal CLK
