Signal DescriptionsMCF5272 ColdFire ® Integrated Microprocessor User’s Manual, Rev. 3Freescale Semiconductor 19-2319.6.12 SDRAM Bank Selects (SDBA[1:0])These outputs are the SDRAM bank select signals.19.6.13 SDRAM Row Address 10 (A10)/A10 Precharge (A10_PRECHG)This output is the SDRAM row address 10 and the precharge strobe.19.7 CPU Clock and Reset SignalsThis section describes clock and reset signals in the CPU.19.7.1 RSTIRSTI is the primary reset input to the device. Asserting RSTI immediately resets the CPU and peripherals.However, the reset of the SDRAM controller and hence SDRAM contents depend on DRESETEN.Asserting RSTI also causes RSTO to be asserted for 32K CPU clock cycles.19.7.2 DRESETENDRESETEN is asserted to indicate that the SDRAM controller is to be reset whenever RSTI asserts. IfDRESETEN is high, RSTI does not affect the SDRAM controller, which continues to refresh externalmemory. This is useful for debug situations where a reset of the device is required without losing datalocated in SDRAM. DRESETEN is normally tied high or low depending on system requirements. It shouldnever be tied to RSTI or RSTO.19.7.3 CPU External Clock (CLKIN)CLKIN should be connected to an external clock oscillator. The CLKIN input frequency can range fromDC to 66 MHz. The frequency input to this signal must be greater than twice the frequency applied at E_TxCLK. The clock frequency applied to CLKIN must exceed 24 MHz when the system uses a USBperipheral.19.7.4 Reset Output (RSTO)Reset output (RSTO) is driven low for 128 CPU clocks when the soft reset bit of the system configurationregister (SCR[SOFTRST]) is set. It is driven low for 32K CPU clocks when the software watchdog timertimes out or when a low input level is applied to RSTI.19.8 Interrupt Request Inputs (INT[6:1])The six interrupt request inputs (INT[6:1]) can generate separate, maskable interrupts on negative edge(high to low) or positive edge (low to high) transitions. In addition to the triggering edge beingprogrammable, the priority can also be programmed. Each interrupt input has a separate programmableinterrupt level.
