MCF5272 ColdFire ® Integrated Microprocessor User’s Manual, Rev. 3Freescale Semiconductor 11-1Chapter 11Ethernet ModuleThis chapter begins with a feature-set overview, a functional block diagram, and transceiver connectioninformation for both MII and seven-wire serial interfaces. The chapter concludes with detaileddescriptions of operation and the programming model.11.1 OverviewThe MCF5272’s integrated fast Ethernet media access controller (MAC) performs the full set of IEEE802.3/Ethernet CSMA/CD media access control and channel interface functions. It requires an externalinterface adaptor and transceiver function to complete the interface to the media.11.1.1 FeaturesThe fast Ethernet controller (FEC) incorporates the following features:• Full compliance with the IEEE 802.3 standard• Support for three different physical interfaces:— 100 Mbps 802.3 media independent interface (MII)— 10 Mbps 802.3 MII— 10 Mbps seven-wire interface• Half-duplex 100-Mbps operation at system clock frequency Š 50 MHz• 448 bytes total on-chip transmit and receive FIFO memory to support a range of bus latenciesNote: the total FIFO size is 448 bytes. It is not intended to hold entire frames but only tocompensate for external bus latency. The FIFO can be partitioned on any 32-bit boundary betweenreceive and transmit, for example, 32 x 56 receive and 32 x 56 transmit.• Retransmission from transmit FIFO following a collision, no processor bus used• Automatic internal flushing of the receive FIFO for runts and collisions with no processor bus use11.2 Module OperationThe FEC is implemented using a combination of hardware and microcode. Figure 11-1 shows a functionalblock diagram of this module.
