ColdFire CoreMCF5272 ColdFire ® Integrated Microprocessor User’s Manual, Rev. 32-24 Freescale Semiconductor2.7.4 Miscellaneous Instruction Execution TimesTable 2-15 lists timings for miscellaneous instructions.sub.l Dy, — 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1) —subi.l #imm,Dx 1(0/0) — — — — — — —subq.l #imm, 1(0/0) 3(1/1) 3(1/1) 3(1/1) 3(1/1) 4(1/1) 3(1/1) —subx.l Dy,Dx 1(0/0) — — — — — — —Table 2-15. Miscellaneous Instruction Execution TimesOpcode Effective AddressRn (An) (An)+ –(An) (d16,An) (d8,An,Xi*SF) (xxx).wl #cpushl (Ax) — 11(0/1) — — — — — —link.w Ay,#imm 2(0/1) — — — — — — —move.w CCR,Dx 1(0/0) — — — — — — —move.w ,CCR 1(0/0) — — — — — — 1(0/0)move.w SR,Dx 1(0/0) — — — — — — —move.w ,SR 7(0/0) — — — — — — 7(0/0)movec Ry,Rc 9(0/1) — — — — — — —movem.l 11 n is the number of registers moved by the MOVEM opcode.,&list — 1+n(n/0) — — 1+n(n/0) — — —movem.l &list, — 1+n(0/n) — — 1+n(0/n) — — —nop 3(0/0) — — — — — — —pea — 2(0/1) — — 2(0/1) 22 PEA execution times are the same for (d16,PC).3(0/1)33 PEA execution times are the same for (d8,PC,Xi*SF).2(0/1) —pulse 1(0/0) — — — — — — —stop #imm — — — — — — — 3(0/0)44 The execution time for STOP is the time required until the processor begins sampling continuously for interrupts.trap #imm — — — — — — — 15(1/2)trapf 1(0/0) — — — — — — —trapf.w 1(0/0) — — — — — — —trapf.l 1(0/0) — — — — — — —unlk Ax 2(1/0) — — — — — — —wddata.l — 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 3(1/0) —wdebug.l — 5(2/0) — — 5(2/0) — — —Table 2-14. Two-Operand Instruction Execution Times (continued)Opcode Effective AddressRn (An) (An)+ –(An) (d16,An) (d8,An,Xi*SF) (xxx).wl #
