SDRAM ControllerMCF5272 ColdFire ® Integrated Microprocessor User’s Manual, Rev. 3Freescale Semiconductor 9-3Figure 9-2 is the pinout of a 16-bit SDRAM in a 54-pin TSOP (thin, small-outline package) package. Sizecan vary from 16–256 Mbits.Figure 9-2. 54-Pin TSOP SDRAM Pin DefinitionSDCLK SDRAM (bus) clock (same frequency as CPU clock). This dedicated output reduces setup and holdtime uncertainty due to process and temperature variations. SDCLK is disabled for SDRAMpower-down mode.SDCLKE SDRAM clock enableSDRAMCS/CS7 SDRAM chip select/CS7. The SDRAM is assigned to CS7 (SDRAMCS) of the device chip selectmodule.SDWE SDRAM write enableTable 9-1. SDRAM Controller Signal Descriptions (continued)Signal DescriptionVDDDQ0VDDDQ1DQ2GNDDQ3DQ4VDDDQ5DQ6GNDDQ7VDDDQMLR/WCASRASCSBA0BA1A10A0A1A2A3VDDGNDDQ15GNDDQ14DQ13VDDDQ12DQ11GNDDQ10DQ9VDDDQ8GNDNCDQMHCLKCKEA12A11A9A8A7A6A5A4GND123456789101112131415161718192021222324252627545352515049484746454443424140393837363534333231302928VDDDQ0VDDDQ1DQ2GNDDQ3DQ4VDDDQ5DQ6GNDDQ7VDDDQMLR/WCASRASCSBA0BA1A10A0A1A2A3VDDVDDDQ0VDDDQ1DQ2GNDDQ3DQ4VDDDQ5DQ6GNDDQ7VDDDQMLR/WCASRASCSBA0BA1A10A0A1A2A3VDDGNDDQ15GNDDQ14DQ13VDDDQ12DQ11GNDDQ10DQ9VDDDQ8GNDNCDQMHCLKCKEA12A11A9A8A7A6A5A4GNDGNDDQ15GNDDQ14DQ13VDDDQ12DQ11GNDDQ10DQ9VDDDQ8GNDNCDQMHCLKCKEA12A11A9A8A7A6A5A4GND256 Mbit128 Mbit64 Mbit
