A/D (Modules C1, C2, C3, C4 & CA)68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014Rev: 2014-12-19-0947 www.naii.com Page 106 of 330A/D (MODULES C1, C2, C3, C4 & CA)Principle of OperationModules C1, C2 and C4 provide up to 10 differential (non-isolated) distinct individual A/D channels for a wide range ofinput voltages (up to 50V, bipolar). Module C3 provides 10channels of direct current (0-25 mA FS range) measurement.Module CA combines six C2 (channels 1-6) and four C3channels (channels 7-10). Each channel utilizes a separate 16-bit A/D converter. Sample rates are programmable (200 KHzmax.) and common for all channels available on the module.Each differential channel includes a second order anti-aliasingfilter and a post filter that has a digitally programmable breakpoint that enables user to field adjust the filtering for eachchannel. All A/D channels are self-calibrating because each channel, on a rotating basis, is automaticallycalibrated to eliminate offset and gain errors. The input range and gain is field programmable for each channel.The ability to set lower voltages for Full Scale Input assures maximum resolution (does not apply to CurrentMeasurement Module C3 which is fixed unipolar, 0-25mA FS). Module C1 provides ‘open wire’ status capability.Open inputs cannot be sensed for other module types because precision scaling input resistor networks areutilized. All inputs are double buffered for immediate data availability. The “Latch” feature permits the user to readall A/D channels at the same time. The module(s) now includes A/D FIFO Buffering for greater control of theincoming signal (data) for analysis and display. When initialized/triggered, the A/D buffer will accept/store the dataat the same rate as the base A/D sampling rate or as a divided multiple as set in the Sample Rate Register.Programmable buffer sample thresholds can be utilized for data flow control.Built-In Test (BIT) / Diagnostic CapabilityThree different tests, one on-line (D2) and two off-line (D0, D3), can be selected:The on-line (D2) test initiates automatic background BIT testing, where each channel is checked to a testaccuracy of 0.2% FS. Any failure triggers an Interrupt (if enabled) with the results available in BIT status register.The testing is totally transparent to the user, requires no external programming, has no effect on the operation ofthis card and can be enabled or disabled via the bus. In addition, all channels are monitored for open input onModule C1.The off-line (D3) test starts an initiated BIT test that disconnects all A/D’s from the I/O and then connects themacross an internal stimulus. Each channel will be checked to a test accuracy of 0.2% FS and monitored for openinputs. Test cycle is completed within 20 seconds and results can be read from the Status registers when D3changes from “1” to “0”. The test can be stopped at any time and requires no user programming and can beenabled or disabled via the bus. A/D Open Circuit monitoring is disabled during D3 testing.An off-line (D0) test is used to check the card and interface. Write “1” to D0 of Test enable register to disconnectall A/D channels from the I/O and to connect them across an internal D/A. Test parameters are controlled by theuser and are entered in the D0 Test Voltage and D0 Test Range registers. The outputs from the A/D channels aremonitored by an internal D/A for proper conversion. External reference voltage is not required.Front End110Wrap-AroundTestD/AAD 1AD 10StateMachineAD Module Block Diagram110Module BusUser Interface
