SSI / Encoder / Quadrature Counter (Module E7)68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014Rev: 2014-12-19-0947 www.naii.com Page 277 of 330InterruptInterrupt Vector RegistersInterrupt Assignment VME Address-Not Used- 03C0SSI_CH_1 (n_Data) 03C2SSI_CH_2 (n_Data) 03C4SSI_CH_3 (n_Data) 03C6SSI_CH_4 (n_Data) 03C8Counter CH1_Match 03CACounter CH2_Match 03CCCounter CH3_Match 03CECounter CH4_Match 03D0Counter CH1 Index_Int 03D2Counter CH2 Index_Int 03D4Counter CH3 Index_Int 03D6Counter CH4 Index_Int 03D8Interval Timer (TC) 03DAMulti_Cycle_Rd 03DC-Not Used- 03DEInterrupts generated from each subsystem, are encoded as indicated and passed through the MOD_BUSinterrupt services to generate a vectored bus interrupt.Interrupt StatusThe interrupt status is read only. This status indicates the state of pending interrupts for this module.Please Note; reading or writing to this register has no effect on the status of any interrupts. Interrupts must be cleared byreading the status at the subsystem level. As an example clearing the interrupt flag for SSI_CH1, the processor would readthe SSI status register for CH1.Bit Symbol Description Access[15] -Not Used- (Read as Zero) 0[14] Multi_Cycle_Rd Multi-Cycle Read Complete r[13] -Not Used- (Read as Zero) 0[12] -Not Used- (Read as Zero) 0[11] -Not Used- (Read as Zero) 0[10] -Not Used- (Read as Zero) 0[9] -Not Used- (Read as Zero) 0[8] Match_CH4 Counter Match Interrupt – CH3 r[7] Match_CH3 Counter Match Interrupt – CH2 r[6] Match_CH2 Counter Match Interrupt – CH1 r[5] Match_CH1 Counter Match Interrupt – CH1 r[4] SSI_CH4 SSI Interrupts – CH4 r[3] SSI_CH3 SSI Interrupts – CH3 r[2] SSI_CH2 SSI Interrupts – CH2 r[1] SSI_CH1 SSI Interrupts – CH1 r[0] -Not Used- (Read as Zero)
