DLV 3 Channel (Module 5*)68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014Rev: 2014-12-19-0947 www.naii.com Page 248 of 330DLV 3 CHANNEL (MODULE 5*)(*See part number designation)Principle of OperationThis Digital-to-LVDT/RVDT (DLV) SimulationModule offers three, 2-wire or 3/4-wire“Programmable” LVDT/RVDT outputs with wrap-around self test. This card can be programmedand re-programmed in the field for any excitationand signal voltage between 2.0 and 28 volts.Operating frequency between 47 Hz and 10 KHzcan be specified (See part number). One excitationinput is supplied for each output. The output formatcan be programmed to simulate either two-wire orthree/four-wire LVDT’s. The transformation ratio(TR), same for each pair of outputs, sets the maximum output voltage with relation to the excitation voltage (TR =Max Output Voltage/Excitation Voltage). Use of a ratiometric design eliminates errors caused by excitationvoltage variations; however, an absolute output (one that does not vary with excitation) can be programmed.New features include a wrap for measuring, of each channel, the output position, current and carrier frequency(Pending). A background calibration feature (pending) will constantly adjust the outputs for load andenvironmental condition.Built-in Test/Diagnostic CapabilityExtensive Built-In-Test (BIT) diagnostics are implemented which include continuous transparent backgroundaccuracy testing as well as user-invoked testing. Two different tests (one on-line and one off-line) can beselected:The on-line (D2) Test initiates automatic background BIT testing (on-line) that checks the output accuracy ofeach channel by comparing the measured output position to the commanded position. This test continuouslychecks each channel individually over the programmed signal range to an accuracy of 0.2% FS. Each DLV Signaloutput and Excitation input is continually monitored. Any failure triggers an Interrupt (if enabled) and the resultsare available in registers. User can periodically clear to 00h and then read Test (D2) verification register again,after 30 seconds, to verify that background bit testing is activated. The testing is totally transparent to the user,requires no external programming, has no effect on the standard operation of this card and can be enabled ordisabled.The off-line (D3) Test initiates a BIT Test that generates and tests 20 different positions to an accuracy of 0.2%.External excitation is required and outputs must be ON. The DLV Status bits will be set to indicate an accuracyproblem. Results are available in the DLV Test Status Registers and if enabled, an interrupt will be generated.The testing requires no external programming and can be initiated or terminated at any time.CAUTION: Outputs must be ON and Excitation supplied during this test and therefore active. Check connectedloads for possible interaction.Wrap LVDT Position (Read)Wrap-around positions are read from the Wrap-around Channel Registers. Each enabled DLV channel ismeasured and can be read from the corresponding Wrap-around Channel Register. The generated result is a 16-bit binary word (or 16-bit 2’s complement word) that represents position. The data is available at any time.Note: In 3/4-wire mode, only channels 1A, 2A need to be read.DLV Channel Excitation VoltageEach individual channel input Excitation voltage “VEXC” is measured and the value reported to a correspondingread register. The input voltage is reported to a resolution of 10 mv rms. The output is in integer decimal format.For example, if channel 1 input signal voltage is 11.8 VRMS, the output measurement word from thecorresponding register would be 1180.Signal andReferenceIsolation12Wrap-AroundTestLVDTDLV 1DLV 2StateMachineDLV Module Block Diagram12Module BusUser Interface
