D/A (Modules F & J, Except J8)68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014Rev: 2014-12-19-0947 www.naii.com Page 127 of 330D/A (MODULES F & J, EXCEPT J8)Principle of OperationTen D/A channels (Modules F1, F3, J3, J5)or four D/A High Current at 100 mA (ModuleF5) channels are provided per module andincludes extensive diagnostics. Overloadedoutputs will be detected, with the resultsdisplayed in a status word. This moduleincorporates major diagnostic capabilitiesthat offer substantial improvements tosystem reliability because user is alerted tomalfunctions within five seconds.The system includes D/A FIFO Buffering forgreater control of the output voltage andsignal data. The FIFO D/A buffer will accept, store and output the voltage once enabled and triggered, forapplications requiring simulation of waveform generation. The data can be “outputted” from the buffer at amaximum D/A Buffer base rate of 390.625 KHz .The thresholds of the buffer can be utilized for data flow control.Built-In Test (BIT) / Diagnostic CapabilityTwo different tests, one on-line (D2) and one off-line (D3), can be selected:The on-line (D2) test initiates automatic background BIT testing, where each channel is checked to a testaccuracy of 0.2% FS and monitored for shorted output. Any failure triggers an Interrupt (if enabled) with theresults available in status registers. The testing is totally transparent to the user, requires no externalprogramming, has no effect on the operation of this card and can be enabled or disabled via the bus.The off-line (D3) test uses an internal A/D that measures all D/A channels while they remain connected to the I/O.Each channel will be checked to a test accuracy of 0.2% FS. Test cycle is completed within 45 seconds andresults can be read from the Status registers when D3 changes from ‘1’ to “0”. The test can be stopped at anytime. This test requires no user programming and can be enabled or disabled via the bus.CAUTION: D/A Outputs are active during D3 test. Check connected loads for interaction. D/A Over-Current (shortcircuit) monitoring is disabled during D3 testing.Data (Write D/A) Output (F1, F3, J3, J5 Modules)If using bi-polar mode, write 16-bit two’s complement word to the channel’s Data register (7FFFh=+FS,8000h=-FS) If using uni-polar mode, write 16-bit binary word to the channel’s Data register (range: 0 toFFFFh=FS).Data (Write D/A) Output (F5 Module Only)If using bi-polar and single ended modes, write 16-bit two’s complement word to the channel’s Data register(range: 7FFFh=+FS, 8000h=-FS) If using unipolar and single ended modes, write 16-bit binary word to thechannel’s Data register (range: 0 to FFFFh=FS).If using bi-polar and differential modes, write 16-bit two's complement word to channel 1 or channel 3's Dataregister (range: 7FFFh=+FS, 8000h=-FS) and the respective channel will go to that voltage. Additionally, theother channel in the pair (channel 1 is paired with channel 2, and channel 3 is paired with channel 4) will go to thetwo's complement of the Data register. Channel 2 and channel 4's Data registers aren't used in this configuration.If using uni-polar and differential modes, write 16-bit binary word to channel 1 or channel 3's Data register (range:0 to FFFFh=FS) and the respective channel will go to Data register / 2 + 7FFFh. Additionally, the other channel inthe pair (channel 1 is paired with channel 2, and channel 3 is paired with channel 4) will go to 7FFFh - (Dataregister / 2). Channel 2 and channel 4's Data registers aren't used in this configuration.MUXStateMachine110Wrap-AroundTestA/DDA 1DA 10ProtectiveCircuitsDA Module Block Diagram101Module BusUser InterfaceCurrent LimitCircuit 1Current LimitCircuit 10MUX101
