Contents - MODEL 68C3
- GENERAL BOARD SPECIFICATION
- SOFTWARE SUPPORT
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- SPECIFICATIONS
- RS-422/485 (Module PC) – Isolated, Four High Speed RS-422 / 485 Serial Communications
- A/D (Module C1) – Ten A/D Channels (1.25 to 10.0 VDC FS) Uni or Bipolar
- A/D (Module C2) – Ten A/D Channels (5.0 to 40.0 VDC FS) Uni or Bipolar
- A/D (Module C3) – Ten A/D Channels (4-25mA)
- A/D (Module C4) – Ten A/D Channels (6.25 to 50.0 VDC FS) Uni or Bipolar
- Specifications applicable to channels 1-6 (40 VDC A/D)
- I/O (Module D7) – Sixteen TTL Channels— Programmable for I/O
- D/A (Module F1) − Ten D/A Outputs ( 10 VDC)
- D/A (Module F5) − Four D/A High Current Outputs ( 20VDC at 100 mA)
- D/A (Module J5) − Ten D/A Outputs ( 2.5 VDC)
- RTD (Module G4) – Six Channel RTD Measurement
- Features
- A/D Channels
- S/D (Module S*) – Four Isolated Synchro/Resolver Measurement Channels
- D/S (Module 6*) –Three Isolated Digital-to-SYN/RSL Ch, 0.25 VA Power Output
- DLV (Module 5*) – Three Isolated DLV Stimulus Channels, LVDT or RVDT Outputs
- SSI Mode
- Input
- C3 ADDRESS CONFIGURATION
- PRODUCT CONFIGURATION AND MEMORY MAP
- C3 CARD-LEVEL MODULE CONFIGURATION and MEMORY MAPPING
- ARINC 429/575 SIX CHANNEL, TX/RX (MODULE A4)
- Receive Operation
- Schedule Transmit Commands
- Interrupt
- Module Factory Defaults
- Tx (Transmit) Buffer (FIFO)
- Rx FIFO (Buffer) Threshold
- Channel Control Low
- Channel Control High
- Channel Status
- Interrupt Enable
- Interrupt Status
- Mailbox (MBOX) Address Register
- Mailbox (MBOX) Data Register
- Transmit Trigger Register
- Transmit Stop Register
- Timestamp Hi + Lo Register
- Memory Page Window
- Rx Match Memory Layout
- DSP Compile Time
- MODULE PCI MEMORY MAP – 6 CHANNEL ARINC COMMUNICATIONS (A4)
- COMMUNICATIONS (MODULES N7 AND N8)
- CANBUS CONTROL AREA NETWORK (MODULE P6, PA)
- P6 Specific CAN A/B Register Descriptions
- Acceptance Mask LO (set per channel) (P6 – CAN A/B Only)
- MSG_ID3
- Data Size
- PA Specific J1939 Register Descriptions
- P6 (CAN A/B) or PA (J1939) Global Register Descriptions
- Comm Status for Channel X (Global)
- Ch X Baud / Bit Timing Register (Global)
- Ch X Baud Rate Prescaler Extension Reg (Global)
- PGN_HI (Global)
- MODULE (P6) CANBUS CAN A/B PCI REGISTER MAP
- MODULE (PA) CANBUS J1939 PCI REGISTER MAP
- FOUR CHANNEL, SERIAL (RS232/422/485) (MODULE P8) / ISOLATED RS-422/RS-485 (MODULE PC)
- Serial Communications Specifications
- Communication Module Factory Defaults: Registers and Delays
- Transmit Buffer
- Number of Words Rx Buffer
- Interface Levels
- Tx-Rx Configuration Low
- Channel Control Extended
- Baud Rate
- Rx Buffer Almost Full
- Rx Buffer Low Watermark
- HDLC Tx Address/Sync Character
- XOFF Character
- FOUR CHANNEL SERIAL COMMUNICATIONS (MODULE P8/PC) PCI MEMORY MAP
- A/D (MODULES C1, C2, C3, C4 & CA)
- Data Read
- D0 Test Voltage
- FIFO Size (per channel)
- Trigger Control (per channel)
- Software Trigger (per channel)
- Test Enable
- Open Status
- Interrupt and Status Register Operation/Clarification
- A/D (MODULES C1, C2, C3 & C4) PCI MEMORY MAP
- I/O DIGITAL TTL/CMOS (MODULE D7)
- Read Input or Output
- Reset Over-Current
- I/O DIGITAL TTL/CMOS (MODULE D7) PCI MEMORY MAP
- DIFFERENTIAL MULTI-MODE TRANSCEIVERS (MODULE D8)
- De-bounce Time
- Input/Output Format
- Interrupt Vectors
- I/O (MODULE D8) PCI MEMORY MAP
- D/A (MODULES F & J, EXCEPT J8)
- D/A Polarity
- Over Current Override
- Words in FIFO
- Sample Rate
- Trigger Control
- Over Current Status
- D/A (MODULE F OR J, EXCEPT J8) PCI MEMORY MAP
- HIGH VOLTAGE D/A (MODULE J8)
- D/A Output Range
- BIT Status Interrupt Enable
- D/A (MODULE J8) PCI MEMORY MAP
- THERMOCOUPLE MEASUREMENT (MODULE G3)
- Temperature
- ADC Data (RAW)
- Compensation Type
- Update Rate
- Appendix A (IEEE 754 Format)
- Appendix B (G3 Optional External Isothermal Block Accessory)
- Optional Accessory NAI P/N ACC-ISO-THERM-BLK1
- THERMOCOUPLE (MODULE G3) PCI MEMORY MAP
- RTD (MODULE G4)
- Resistance
- Wire Lead Resistance Compensation
- RTD (MODULE G4) PCI MODULE REGISTER MAP
- LOAD/STRAIN (MODULE G5)
- data2.
- Range
- Chop Enable
- Filter Configuration
- BUSY
- Open Status Interrupt Enable
- Appendix (G5)
- STRAIN GAGE (MODULE G5) PCI MODULE MEMORY REGISTER MAP
- I/O DISCRETE (MODULE K6 VER. 4 )
- Threshold Programming
- Upper Threshold
- Read I/O
- Current for Source/Sink
- Write Output
- Read Output Voltage
- I/O Discrete (Module K6) – Addendum A (PWM Enhanced Function)
- PWM/Timer Period
- PWM/TIMER Configuration (Polarity)
- PWM/TIMER Mode Enable
- DISCRETE (MODULE K6 VER. 4) PCI MODULE MEMORY REGISTER MAP
- I/O DISCRETE (MODULE K7)
- Input/Switch Interface
- Max High Threshold
- Read Switch Current (Average)
- DISCRETE (MODULE K7) PCI MODULE MEMORY REGISTER MAP
- I/O RELAY (MODULE KN, KL)
- Status, BIT Fault
- I/O RELAY (MODULE KN, KL) PCI MEMORY MAP
- DISCRETE/ANALOG TO DIGITAL COMBINATION (MODULE KA)
- KA Module A/D Specific Functions
- KA Module Discrete I/O Specific Functions
- Status Interrupt Enable
- DISCRETE / A-D COMBINATION (MODULE KA) PCI MEMORY MAP
- LVDT MEASUREMENT (MODULE L*)
- Various LVDT Configurations
- Bandwidth (BW)
- Input Reference Frequency Measurement
- Reference Status
- OSC (Onboard) Excitation Set Frequency
- Interrupt Vector
- Hi-Threshold
- Buffer Data Type
- Status, BIT Fail
- LVDT (MODULE L) PCI MEMORY MAP
- SYNCHRO/RESOLVER MEASUREMENT (MODULE S*)
- Data
- Bandwidth Select
- Test (D2) Verify
- Angle Δ
- A & B Resolution
- Signal Status
- Signal Status Interrupt Enable
- S/D Angle Change (Angle Δ Alert) Interrupt Enable
- Low-Threshold
- Trigger Mode
- S/D (MODULE S) PCI MEMORY MAP
- D/S THREE CHANNEL (MODULE 6*)
- Signal Loss Threshold
- D/S Write Angle – Two Speed
- D/S Rotation Status
- D/S Ratio 1/2
- D/S Module Power Enable
- D/S Status, Phase Lock Loss
- Reference Loss Interrupt Enable
- OSC (Optional Onboard Reference Supply) Set Voltage
- D/S 3 CHANNEL (6*) PCI MODULE MEMORY MAP
- DLV 3 CHANNEL (MODULE 5*)
- DLV Channel Signal Voltage
- Status, Signal Loss
- DLV Module Power Enable
- DLV Status, Excitation
- DLV Status, BIT Test
- Phase Lock Loss Interrupt Enable
- CH DLV (5*) (PCI) MODULE MEMORY MAP
- SSI / ENCODER / QUADRATURE COUNTER (MODULE E7)
- Channel Inputs
- Standard SSI Interface Controller Mode
- Listen Only Mode
- Parity
- Control Register 0
- Control Register 1
- SSI Status
- Counter Modes
- Index Control Modes (ICM)
- Special Count Mode
- Internal Clock Prescaler
- Counter Status Register
- Up/Down Count
- Interval Timer Control
- Global Control Registers
- Multiple Channel Read
- Interrupt Enable Register
- CPLD (Module Configuration Registers)
- CPLD Register Low
- Differential (DE) / Single-Ended (SE) Selection
- Appendix A – Quadrature (A-Quad-B) Discussion
- Appendix B – Operation Mode Signal Details
- FOUR CHANNEL SSI/ENCODER (MODULE E7) PCI MEMORY MAP
- ISOLATED ±15V DC/DC CONVERTER (MODULE V1, V2)
- Registers
- Output Current (V-)
- MODULE (V*), DUAL ±15V DC/DC CONVERTER, PCI MEMORY REGISTER MAP
- REFERENCE (MODULE W*)
- Reference Voltage
- REFERENCE (MODULE W*) PCI MEMORY MAP
- MODULE IDENTIFICATION
- Module FPGA Revision
- GENERAL USE REGISTER MEMORY MAP
- Platform
- Date Code
- Board Ready
- Design Version
- Customer Defined Register Allocation
- ETHERNET
- Type Codes Summary
- C3 CONNECTOR/PIN-OUT INFORMATION
- Front Panel (J1, J2) (Connector Placement and Orientation)
- Rear I/O VPX Connectors P0 – P2
- Rear I/O Utility Plane (P0)
- Rear I/O Data/Control Planes (P1 Continued)
- Rear I/O Summary
- SLOT 1 – Analog and Digital I/O Modules (User Defined I/O Pin-Outs)
- SLOT 1 –Digital I/O Modules (User Defined I/O Pin-Outs)
- SLOT 1 – Position/Motion Control I/O Modules (User Defined I/O Pin-Outs)
- SLOT 1 – Communications I/O Modules (User Defined I/O Pin-Outs)
- SLOT 2 – Analog I/O Modules (User Defined I/O Pin-Outs)
- SLOT 2 –Digital I/O Modules (User Defined I/O Pin-Outs)
- SLOT 2 – Position/Motion Control I/O Modules (User Defined I/O Pin-Outs)
- SLOT 2 – Communications Modules (User Defined I/O Pin-Outs)
- SLOT 3 – Onboard Reference or Multi-Function Combo (User Defined I/O Pin-Outs)
- Connector Signal/Pin-Out Notes
- PART NUMBER DESIGNATION
- Part Number Notes
- Channel D/S Module Code Table
- Channel DLV Module Code Table
- REVISION
- 68C3 Operations Manual
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Module PCI Memory Map – 6 Channel ARINCCommunications (A4)68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014Rev: 2014-12-19-0947 www.naii.com Page 71 of 330MODULE PCI MEMORY MAP – 6 CHANNEL ARINC COMMUNICATIONS (A4)Module Length = 800h000 Tx Buffer Ch 1 W 120 Tx Buffer Ch 4 W 258 RECEIVE DATA UNBUFFERED R008 Rx Buffer Ch 1 R 128 Rx Buffer Ch 4 R010 Rx FIFO Threshold Ch 1 R/W 130 Rx FIFO Threshold Ch 4 R/W 260 TX TRIGGER REG W014 Tx FIFO Threshold Ch 1 R/W 134 Tx FIFO Threshold Ch 4 R/W 264 TX PAUSE REG W018 Rx FIFO Level Ch 1 R 138 Rx FIFO Level Ch 4 R 268 TX STOP REG W01C Tx FIFO Level Ch 1 R 13C Tx FIFO Level Ch 4 R 26C TIMESTAMP CONTROL REG W020 Channel Control Low Ch 1 R/W 140 Channel Control Low Ch 4 R/W 270 TIMESTAMP HIGH REG R024 Channel Control High Ch 1 R/W 144 Channel Control High Ch 4 R/W 274 TIMESTAMP LOW REG R028 Channel Status Ch 1 R/W 148 Channel Status Ch 4 R/W 278 MODULE RESET W02C Channel Interrupt Enable Ch 1 R/W 14C Channel Interrupt Enable Ch 4 R/W030 Channel Interrupt Status Ch 1 R/W 150 Channel Interrupt Status Ch 4 R/W 3FC MEMORY PAGE REG R/W034 Channel Tx FIFO Rate High Ch 1 R/W 154 Channel Tx FIFO Rate High Ch 4 R/W 400 MEMORY WINDOW BOTTOM R/W038 Channel Tx FIFO Rate Low Ch 1 R/W 158 Channel Tx FIFO Rate Low Ch 4 R/W 5FC MEMORY WINDOW TOP R/W03C MBOX Addr Reg Ch 1 R/W 15C MBOX Addr Reg Ch 4 R/W040 MBOX StatusWd Ch 1 R 160 MBOX StatusWd Ch4 R 700 BIT STATUS R044 MBOX DataWd Ch 1 R 164 MBOX DataWd Ch 4 R720 DSP Compile Time – Begin R060 Tx Buffer Ch 2 W 180 Tx Buffer Ch 5 W 74C DSP Compile Time – End R068 Rx Buffer Ch 2 R 188 Rx Buffer Ch 5 R070 Rx FIFO Threshold Ch 2 R/W 190 Rx FIFO Threshold Ch 5 R/W 768 Module Design Version R074 Tx FIFO Threshold Ch2 R/W 194 Tx FIFO Threshold Ch 5 R/W 76C Module Design Revision R078 Rx FIFO Level Ch 2 R 198 Rx FIFO Level Ch 5 R 770 DSP Rev R07C Tx FIFO Level Ch 2 R 19C Tx FIFO Level Ch 5 R 774 FPGA Rev R080 Channel Control Low Ch 2 R/W 1A0 Channel Control Low Ch 5 R/W 778 Module ID R084 Channel Control High Ch 2 R/W 1A4 Channel Control High Ch 5 R/W088 Channel Status Ch 2 R/W 1A8 Channel Status Ch 5 R/W 784 FPGA Int 1 Ch 1 Vector R/W08C Channel Interrupt Enable Ch 2 R/W 1AC Channel Interrupt Enable Ch 5 R/W 788 FPGA Int 2 Ch 2 Vector R/W090 Channel Interrupt Status Ch 2 R/W 1B0 Channel Interrupt Status Ch 5 R/W 78C FPGA Int 3 Ch 3 Vector R/W094 Channel Tx FIFO Rate High Ch2 R/W 1B4 Channel Tx FIFO Rate High Ch 5 R/W 790 FPGA Int 4 Ch 4 Vector R/W098 Channel Tx FIFO Rate Low Ch 2 R/W 1B8 Channel Tx FIFO Rate Low Ch 5 R/W 794 FPGA Int 5 Ch 5 Vector R/W09C MBOX Addr Reg Ch 2 R/W 1BC MBOX Addr Reg Ch 5 R/W 798 FPGA Int 6 Ch 6 Vector R/W0A0 MBOX StatusWd Ch 2 R 1C0 MBOX StatusWd Ch 5 R0A4 MBOX DataWd Ch 2 R 1C4 MBOX DataWd Ch 5 R0C0 Tx Buffer Ch 3 W 1E0 Tx Buffer Ch 6 W0C8 Rx Buffer Ch 3 R 1E8 Rx Buffer Ch 6 R0D0 Rx FIFO Threshold Ch 3 R/W 1F0 Rx FIFO Threshold Ch 6 R/W0D4 Tx FIFO Threshold Ch 3 R/W 1F4 Tx FIFO Threshold Ch 6 R/W0D8 Rx FIFO Level Ch 3 R 1F8 Rx FIFO Level Ch 6 R0DC Tx FIFO Level Ch 3 R 1FC Tx FIFO Level Ch 6 R0E0 Channel Control Low Ch 3 R/W 200 Channel Control Low Ch 6 R/W0E4 Channel Control High Ch 3 R/W 204 Channel Control High Ch 6 R/W0E8 Channel Status Ch 3 R/W 208 Channel Status Ch 6 R/W0EC Channel Interrupt Enable Ch 3 R/W 20C Channel Interrupt Enable Ch 6 R/W0F0 Channel Interrupt Status Ch 3 R/W 210 Channel Interrupt Status Ch 6 R/W0F4 Channel Tx FIFO Rate High Ch 3 R/W 214 Channel Tx FIFO Rate High Ch 6 R/W0F8 Channel Tx FIFO Rate Low Ch 3 R/W 218 Channel Tx FIFO Rate Low Ch 6 R/W0FC MBOX Addr Reg Ch 3 R/W 21C MBOX Addr Reg Ch 6 R/W100 MBOX StatusWd Ch3 R 220 MBOX StatusWd Ch 6 R104 MBOX DataWd Ch 3 R 224 MBOX DataWd Ch 6 R
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