ARINC 429/575 Six Channel, Tx/Rx (Module A4)68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014Rev: 2014-12-19-0947 www.naii.com Page 68 of 330Memory Page WindowType: unsigned integer wordRange: 0 to FFFFhRead/Write: R/WInitialized Value: N/AAccess the 128 word page of memory pointed to by Memory Page Register by reading or writing to 200h + offset,where offset is 0 to FEh in increments of 2 since these are 16-bit word accesses, not byte accesses.Tx Message Memory FormatType: unsigned integer wordRange: 0 to FFFFhRead/Write: R/WInitialized Value: N/AThis memory is shared with the Tx FIFO memory and is only available in Tx Schedule mode. The internalmemory is 256 deep and 32 bits wide but is accessed via the 16 bit data bus as 512 x 16. Writes to a memorylocation must always be sequentially written with the upper then lower 16 bits since the data is internally bufferedand written to memory as a 32 bit word. When reading back a memory location, the memory looks like a 512 x 16memory and the upper 16 bits is read from the even locations and the lower 16 from the odd locations. Thismemory is also used to hold the 20 bit gap time value for the Gap and FixedGap commands in Tx Schedulemode. Values of 4 or less for the gap time are invalid. Each LSB equals one bit period of time, i.e. 10 us in Highspeed and 80 us in Low speed.REGISTER D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FUNCTIONTX MESSAGEMEMORY D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 ARINC UPPER 16D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 ARINC LOWER 16X X X X X X X X X X X X G19 G18 G17 G16 GAP TIME UPPER 4G15 G14 G13 G12 G11 G10 G9 G8 G7 G6 G5 G4 G3 G2 G1 G0 GAP TIME LOWER 16Gap time values < 4 are invalid.Tx Schedule Program Memory FormatType: unsigned integer wordRange: 0 to FFFFhRead/Write: R/WInitialized Value: N/AREGISTER D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FUNCTIONTX SCHEDULEMEMORY 0 0 0 0 X X X X X X X X X X X X STOP CMD0 0 0 1 X X X X MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0 MESSAGE CMD10 0 1 0 X X X X MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0 GAP CMD10 0 1 1 X X X X MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0 FIXEDGAP CMD10 1 0 0 X X X X X X X X X X X X PAUSE CMD0 1 0 1 X X X X X X X X X X X X SCH INTERRUPT CMD0 1 1 0 X X X SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 JUMP CMD20 1 1 1 X X X X X X X X X X X X RESERVED1 X X X X X X X X X X X X X X X RESERVEDNote 1: MA7-MA0 = Address of Tx Message memory organized as 256x32.Note 2: SA8-SA0 = Address of Tx Schedule memory organized as 512x16.
