LVDT Measurement (Module L*)68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014Rev: 2014-12-19-0947 www.naii.com Page 209 of 330LVDT MEASUREMENT (MODULE L*)*Indicates wide selection. (See part number designation.)Principle of Operation (LVDT)The LVDT Module provides four isolatedmeasurement channels, programmable with 2, 3and 4 wire interface capability. Typically theprimary is excited by an AC source, causing amagnetic flux to be generated within thetransducer. Voltages are induced in the twosecondaries, with the magnitude varying with theposition of the core. Usually, the secondaries areconnected in series opposition, causing a netoutput voltage of zero when the core is at theelectrical center. When the core is displaced ineither direction from center the voltage increaseslinearly either in phase or out of phase with theexcitation depending on the direction.Interfacing LVDT to ConverterTwo common connection methods are:1. Primary as reference (two-wire system)2. Derived reference (three/four-wire LVDT)2-Wire SystemThis method of connection converts the widest range of LVDT sensors and is the most sensitive to excitationvoltage variations, temperature and phase shift effects. This system solves the identity V / Vexc.3/4-Wire SystemThe LVDT is again excited from the primary side, but the converter reference is the sum of A + B that hasconstant amplitude for changing core displacement. This system is insensitive to temperature effects, phase shiftsand oscillator instability and solves the identity (A-B) / (A+B).Built-In Test (BIT) / Diagnostic CapabilityThis board incorporates major diagnostics that offer substantial improvements to system reliability because theuser is alerted to channel malfunction. This approach reduces bus traffic, because the Status Registers need notbe constantly polled. Three different tests (one on-line and two off-line) can be selected.The On-line D2 Test initiates automatic background BIT testing (on-line). Each channel is checked over theprogrammed signal range to a measuring accuracy of 0.1% FS, and each Signal and Excitation is monitored. Anyfailure triggers an Interrupt (if enabled) and the results are available in registers. User can periodically clear to 00hand then read Test (D2) verification register again, after 1 second, to verify that background bit testing isactivated. The testing is totally transparent to the user, requires no external programming, has no effect on thestandard operation of this card and can be enabled or disabled.The Off-line D3 Test, if enabled, starts an initiated BIT Test that disconnects all channels from the outsideworld and connects them across an internal stimulus that generates and measures multiple voltages to a testaccuracy of 0.1%FS (offline). External excitation is not required. Any failure triggers an interrupt (if enabled) andresults can be read from registers. The testing requires no external programming and can be initiated orterminated.The Off-line D0 Test is used to check the card and the system interface. All channels are disconnected fromthe outside world (offline), allowing user to write any number of input positions to the card and then read the datafrom the interface. External excitation is not required.
