I/O Discrete (Module K6 Ver. 4)68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014Rev: 2014-12-19-0947 www.naii.com Page 181 of 330I/O Discrete (Module K6) – Addendum A (PWM Enhanced Function)DescriptionA new feature (termed “PWM/Timer Mode”) for the K6 (ver. 4) (GEN3 and higher platforms only) has beenimplemented (applies to platforms with DOM code 1327 (year-week) and higher - PWM support presentlyapplies only to K6 version 4 (rev D) with K6 FPGA rev 5 or later (may be queried from card)). This newfeature will provide an ‘automatic’ signal output (pulse train), based upon a programmable period and “on-time”.The PWM control capability will allow the user/programmer to initialize/trigger/control automatic pulse traingeneration from the K6 channel(s) which greatly reduces software control overhead.The purpose of this enhanced function addendum is to provide detailed information to understand and utilize thenew enhanced function proposed expressly for the K6 module discrete I/O output channel operation. The newfunction is termed “PWM/Timer Mode” and the definition and operation is contained within this document.Features Programmable PWM/Timer period (sets total pulse period) Programmable PWM/Timer pulse width (sets pulse on-time) Programmable PWM/Timer polarity (on-time “high” or “low” definition) Programmable PWM/Timer mode select (feature “ON” or “OFF”) Programmable PWM/Timer mode enable (trigger)Operational Control Registers:By default, the card is powered-up in the “normal” mode (meaning standard operation of all channels). Referencethe Specification/Operation Manual of the appropriate platforms.Note: It is recommended that ‘default’ operational parameters are not ‘relied’ upon power-up and any/all functionalparameters/settings are initialized.Note: Function register offsets provided are for VME 16-bit data addressing. For cPCI/PCI/PCIe/SRIO 32-bit addressing,multiply the noted listed/defined register offsets by 2.Operational notes/considerations:High or Low side drive modes is recommended (with appropriate internal or external pull down/up respectively) ifprecise timing is required or for relatively short duration pulses <100 usec.Push-pull mode may be utilized, however, due to implementation of a non-driven safety period required topreclude conflicting push/pull drive (break-before-make), the output is left “un-driven” for a period of approximately80 usec. on each (H-L) or (L-H) transition.For any drive mode (low-side, high-side (w/ appropriate pull-up/down) or push-pull); when the polarity bit is set to“0” (default) the pulse width will be defined as low-going. When the polarity bit is set to “1” the pulse width will bedefined as high-going. This function is also related to “PWM/Timer Period and Pulse Width”. (Reference figure(1.), Timing Diagram).
