North Atlantic 68C3 Operation Manual

Contents

MODEL 68C3
GENERAL BOARD SPECIFICATION
SOFTWARE SUPPORT
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
SPECIFICATIONS
RS-422/485 (Module PC) – Isolated, Four High Speed RS-422 / 485 Serial Communications
A/D (Module C1) – Ten A/D Channels (1.25 to 10.0 VDC FS) Uni or Bipolar
A/D (Module C2) – Ten A/D Channels (5.0 to 40.0 VDC FS) Uni or Bipolar
A/D (Module C3) – Ten A/D Channels (4-25mA)
A/D (Module C4) – Ten A/D Channels (6.25 to 50.0 VDC FS) Uni or Bipolar
Specifications applicable to channels 1-6 (40 VDC A/D)
I/O (Module D7) – Sixteen TTL Channels— Programmable for I/O
D/A (Module F1) − Ten D/A Outputs (  10 VDC)
D/A (Module F5) − Four D/A High Current Outputs (  20VDC at 100 mA)
D/A (Module J5) − Ten D/A Outputs (  2.5 VDC)
RTD (Module G4) – Six Channel RTD Measurement
Features
A/D Channels
S/D (Module S*) – Four Isolated Synchro/Resolver Measurement Channels
D/S (Module 6*) –Three Isolated Digital-to-SYN/RSL Ch, 0.25 VA Power Output
DLV (Module 5*) – Three Isolated DLV Stimulus Channels, LVDT or RVDT Outputs
SSI Mode
Input
C3 ADDRESS CONFIGURATION
PRODUCT CONFIGURATION AND MEMORY MAP
C3 CARD-LEVEL MODULE CONFIGURATION and MEMORY MAPPING
ARINC 429/575 SIX CHANNEL, TX/RX (MODULE A4)
Receive Operation
Schedule Transmit Commands
Interrupt
Module Factory Defaults
Tx (Transmit) Buffer (FIFO)
Rx FIFO (Buffer) Threshold
Channel Control Low
Channel Control High
Channel Status
Interrupt Enable
Interrupt Status
Mailbox (MBOX) Address Register
Mailbox (MBOX) Data Register
Transmit Trigger Register
Transmit Stop Register
Timestamp Hi + Lo Register
Memory Page Window
Rx Match Memory Layout
DSP Compile Time
MODULE PCI MEMORY MAP – 6 CHANNEL ARINC COMMUNICATIONS (A4)
COMMUNICATIONS (MODULES N7 AND N8)
CANBUS CONTROL AREA NETWORK (MODULE P6, PA)
P6 Specific CAN A/B Register Descriptions
Acceptance Mask LO (set per channel) (P6 – CAN A/B Only)
MSG_ID3
Data Size
PA Specific J1939 Register Descriptions
P6 (CAN A/B) or PA (J1939) Global Register Descriptions
Comm Status for Channel X (Global)
Ch X Baud / Bit Timing Register (Global)
Ch X Baud Rate Prescaler Extension Reg (Global)
PGN_HI (Global)
MODULE (P6) CANBUS CAN A/B PCI REGISTER MAP
MODULE (PA) CANBUS J1939 PCI REGISTER MAP
FOUR CHANNEL, SERIAL (RS232/422/485) (MODULE P8) / ISOLATED RS-422/RS-485 (MODULE PC)
Serial Communications Specifications
Communication Module Factory Defaults: Registers and Delays
Transmit Buffer
Number of Words Rx Buffer
Interface Levels
Tx-Rx Configuration Low
Channel Control Extended
Baud Rate
Rx Buffer Almost Full
Rx Buffer Low Watermark
HDLC Tx Address/Sync Character
XOFF Character
FOUR CHANNEL SERIAL COMMUNICATIONS (MODULE P8/PC) PCI MEMORY MAP
A/D (MODULES C1, C2, C3, C4 & CA)
Data Read
D0 Test Voltage
FIFO Size (per channel)
Trigger Control (per channel)
Software Trigger (per channel)
Test Enable
Open Status
Interrupt and Status Register Operation/Clarification
A/D (MODULES C1, C2, C3 & C4) PCI MEMORY MAP
I/O DIGITAL TTL/CMOS (MODULE D7)
Read Input or Output
Reset Over-Current
I/O DIGITAL TTL/CMOS (MODULE D7) PCI MEMORY MAP
DIFFERENTIAL MULTI-MODE TRANSCEIVERS (MODULE D8)
De-bounce Time
Input/Output Format
Interrupt Vectors
I/O (MODULE D8) PCI MEMORY MAP
D/A (MODULES F & J, EXCEPT J8)
D/A Polarity
Over Current Override
Words in FIFO
Sample Rate
Trigger Control
Over Current Status
D/A (MODULE F OR J, EXCEPT J8) PCI MEMORY MAP
HIGH VOLTAGE D/A (MODULE J8)
D/A Output Range
BIT Status Interrupt Enable
D/A (MODULE J8) PCI MEMORY MAP
THERMOCOUPLE MEASUREMENT (MODULE G3)
Temperature
ADC Data (RAW)
Compensation Type
Update Rate
Appendix A (IEEE 754 Format)
Appendix B (G3 Optional External Isothermal Block Accessory)
Optional Accessory NAI P/N ACC-ISO-THERM-BLK1
THERMOCOUPLE (MODULE G3) PCI MEMORY MAP
RTD (MODULE G4)
Resistance
Wire Lead Resistance Compensation
RTD (MODULE G4) PCI MODULE REGISTER MAP
LOAD/STRAIN (MODULE G5)
data2.
Range
Chop Enable
Filter Configuration
BUSY
Open Status Interrupt Enable
Appendix (G5)
STRAIN GAGE (MODULE G5) PCI MODULE MEMORY REGISTER MAP
I/O DISCRETE (MODULE K6 VER. 4 )
Threshold Programming
Upper Threshold
Read I/O
Current for Source/Sink
Write Output
Read Output Voltage
I/O Discrete (Module K6) – Addendum A (PWM Enhanced Function)
PWM/Timer Period
PWM/TIMER Configuration (Polarity)
PWM/TIMER Mode Enable
DISCRETE (MODULE K6 VER. 4) PCI MODULE MEMORY REGISTER MAP
I/O DISCRETE (MODULE K7)
Input/Switch Interface
Max High Threshold
Read Switch Current (Average)
DISCRETE (MODULE K7) PCI MODULE MEMORY REGISTER MAP
I/O RELAY (MODULE KN, KL)
Status, BIT Fault
I/O RELAY (MODULE KN, KL) PCI MEMORY MAP
DISCRETE/ANALOG TO DIGITAL COMBINATION (MODULE KA)
KA Module A/D Specific Functions
KA Module Discrete I/O Specific Functions
Status Interrupt Enable
DISCRETE / A-D COMBINATION (MODULE KA) PCI MEMORY MAP
LVDT MEASUREMENT (MODULE L*)
Various LVDT Configurations
Bandwidth (BW)
Input Reference Frequency Measurement
Reference Status
OSC (Onboard) Excitation Set Frequency
Interrupt Vector
Hi-Threshold
Buffer Data Type
Status, BIT Fail
LVDT (MODULE L) PCI MEMORY MAP
SYNCHRO/RESOLVER MEASUREMENT (MODULE S*)
Data
Bandwidth Select
Test (D2) Verify
Angle Δ
A & B Resolution
Signal Status
Signal Status Interrupt Enable
S/D Angle Change (Angle Δ Alert) Interrupt Enable
Low-Threshold
Trigger Mode
S/D (MODULE S) PCI MEMORY MAP
D/S THREE CHANNEL (MODULE 6*)
Signal Loss Threshold
D/S Write Angle – Two Speed
D/S Rotation Status
D/S Ratio 1/2
D/S Module Power Enable
D/S Status, Phase Lock Loss
Reference Loss Interrupt Enable
OSC (Optional Onboard Reference Supply) Set Voltage
D/S 3 CHANNEL (6*) PCI MODULE MEMORY MAP
DLV 3 CHANNEL (MODULE 5*)
DLV Channel Signal Voltage
Status, Signal Loss
DLV Module Power Enable
DLV Status, Excitation
DLV Status, BIT Test
Phase Lock Loss Interrupt Enable
CH DLV (5*) (PCI) MODULE MEMORY MAP
SSI / ENCODER / QUADRATURE COUNTER (MODULE E7)
Channel Inputs
Standard SSI Interface Controller Mode
Listen Only Mode
Parity
Control Register 0
Control Register 1
SSI Status
Counter Modes
Index Control Modes (ICM)
Special Count Mode
Internal Clock Prescaler
Counter Status Register
Up/Down Count
Interval Timer Control
Global Control Registers
Multiple Channel Read
Interrupt Enable Register
CPLD (Module Configuration Registers)
CPLD Register Low
Differential (DE) / Single-Ended (SE) Selection
Appendix A – Quadrature (A-Quad-B) Discussion
Appendix B – Operation Mode Signal Details
FOUR CHANNEL SSI/ENCODER (MODULE E7) PCI MEMORY MAP
ISOLATED ±15V DC/DC CONVERTER (MODULE V1, V2)
Registers
Output Current (V-)
MODULE (V*), DUAL ±15V DC/DC CONVERTER, PCI MEMORY REGISTER MAP
REFERENCE (MODULE W*)
Reference Voltage
REFERENCE (MODULE W*) PCI MEMORY MAP
MODULE IDENTIFICATION
Module FPGA Revision
GENERAL USE REGISTER MEMORY MAP
Platform
Date Code
Board Ready
Design Version
Customer Defined Register Allocation
ETHERNET
Type Codes Summary
C3 CONNECTOR/PIN-OUT INFORMATION
Front Panel (J1, J2) (Connector Placement and Orientation)
Rear I/O VPX Connectors P0 – P2
Rear I/O Utility Plane (P0)
Rear I/O Data/Control Planes (P1 Continued)
Rear I/O Summary
SLOT 1 – Analog and Digital I/O Modules (User Defined I/O Pin-Outs)
SLOT 1 –Digital I/O Modules (User Defined I/O Pin-Outs)
SLOT 1 – Position/Motion Control I/O Modules (User Defined I/O Pin-Outs)
SLOT 1 – Communications I/O Modules (User Defined I/O Pin-Outs)
SLOT 2 – Analog I/O Modules (User Defined I/O Pin-Outs)
SLOT 2 –Digital I/O Modules (User Defined I/O Pin-Outs)
SLOT 2 – Position/Motion Control I/O Modules (User Defined I/O Pin-Outs)
SLOT 2 – Communications Modules (User Defined I/O Pin-Outs)
SLOT 3 – Onboard Reference or Multi-Function Combo (User Defined I/O Pin-Outs)
Connector Signal/Pin-Out Notes
PART NUMBER DESIGNATION
Part Number Notes
Channel D/S Module Code Table
Channel DLV Module Code Table
REVISION
68C3 Operations Manual

North Atlantic 68C3 Operation Manual Manual pdf 312 page image

68C3 Connector/Pin-Out Information68C3 Operations Manual North Atlantic Industries, Inc. 12/19/2014Rev: 2014-12-19-0947 www.naii.com Page 312 of 330Rear I/O Summary:P0 - Utility plane. Contains the following signal definitions:Power: Primary +5V, +/- 12V and System GNDGeographical Address Pins: GA0# - GA4#, GAP#Card reset: SYSRST# signalP1 - Defined as primarily Data/Control Planes (User defined I/O secondary)High Speed Switched Fabric Interface: One ultra-thin pipe option (PCIe (x1) or SRIO (1x)).Ethernet: Dual Gig-E port option(s) are available and defined(see part number)P2 - User defined I/O (primary)

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